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| author | Ivan Kosarev <ivan.kosarev@amd.com> | 2023-08-26 17:22:37 -0400 |
|---|---|---|
| committer | Brad Smith <brad@comstyle.com> | 2023-08-26 17:22:37 -0400 |
| commit | 6b2cb3bfaa7b79fd12a6a5bb949031268285dd09 (patch) | |
| tree | eab36fa89ec9210e3de533acb7da8dad48321efb /llvm/lib/Target/XCore | |
| parent | 3891c8d23e41c97815b49d947459daac541f1f97 (diff) | |
| download | llvm-6b2cb3bfaa7b79fd12a6a5bb949031268285dd09.zip llvm-6b2cb3bfaa7b79fd12a6a5bb949031268285dd09.tar.gz llvm-6b2cb3bfaa7b79fd12a6a5bb949031268285dd09.tar.bz2 | |
[XCore] Remove unused TableGen classes and multiclasses
And warn on them from now on.
Reviewed By: nigelp-xmos
Differential Revision: https://reviews.llvm.org/D153533
Diffstat (limited to 'llvm/lib/Target/XCore')
| -rw-r--r-- | llvm/lib/Target/XCore/CMakeLists.txt | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreInstrInfo.td | 19 |
2 files changed, 1 insertions, 20 deletions
diff --git a/llvm/lib/Target/XCore/CMakeLists.txt b/llvm/lib/Target/XCore/CMakeLists.txt index 447f5c5..c759acc 100644 --- a/llvm/lib/Target/XCore/CMakeLists.txt +++ b/llvm/lib/Target/XCore/CMakeLists.txt @@ -4,7 +4,7 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv) -tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel) +tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities) tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info) tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info) diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td index de1fb60..57158e1 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -242,17 +242,6 @@ class F3R_np<bits<5> opc, string OpcStr> : // Three operand long /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. -multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, - SDNode OpNode> { - def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; - def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; -} - -/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, SDNode OpNode> { def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), @@ -305,14 +294,6 @@ multiclass FU6_LU6_np<bits<10> opc, string OpcStr> { def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; } -// Two operand short - -class F2R_np<bits<6> opc, string OpcStr> : - _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), - !strconcat(OpcStr, " $dst, $b"), []>; - -// Two operand long - //===----------------------------------------------------------------------===// // Pseudo Instructions //===----------------------------------------------------------------------===// |