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author | Luke Lau <luke@igalia.com> | 2024-02-26 19:33:44 +0800 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-02-26 19:33:44 +0800 |
commit | b4b490496ab8994fee41005471d075812bdb3a65 (patch) | |
tree | 40418d5d2551061e5dbd61515672989389c48214 /llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | |
parent | bb87c914fec6526fbda81991ce0d35e60040ab9f (diff) | |
download | llvm-b4b490496ab8994fee41005471d075812bdb3a65.zip llvm-b4b490496ab8994fee41005471d075812bdb3a65.tar.gz llvm-b4b490496ab8994fee41005471d075812bdb3a65.tar.bz2 |
[RISCV] Fix insert_subvector with fixed vector type creating invalid node (#82975)
If the vector type is a fixed vector type, we convert it to a container
scalable vector type to compute its reg class. But we need to keep the
old
fixed type so we create a result node with the same type.
This code path is currently dead so I haven't been able to create a test
case
for it. But I have an upcoming patch for insert_subvector lowering that
will
exercise this.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index c922098..1b8c143 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -2066,14 +2066,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { assert(Idx == 0 && V.isUndef()); SubVecContainerVT = TLI.getContainerForFixedLengthVector(SubVecVT); } + MVT ContainerVT = VT; if (VT.isFixedLengthVector()) - VT = TLI.getContainerForFixedLengthVector(VT); + ContainerVT = TLI.getContainerForFixedLengthVector(VT); const auto *TRI = Subtarget->getRegisterInfo(); unsigned SubRegIdx; std::tie(SubRegIdx, Idx) = RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs( - VT, SubVecContainerVT, Idx, TRI); + ContainerVT, SubVecContainerVT, Idx, TRI); // If the Idx hasn't been completely eliminated then this is a subvector // insert which doesn't naturally align to a vector register. These must @@ -2093,7 +2094,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { // If we haven't set a SubRegIdx, then we must be going between // equally-sized LMUL groups (e.g. VR -> VR). This can be done as a copy. if (SubRegIdx == RISCV::NoSubRegister) { - unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(VT); + unsigned InRegClassID = + RISCVTargetLowering::getRegClassIDForVecVT(ContainerVT); assert(RISCVTargetLowering::getRegClassIDForVecVT(SubVecContainerVT) == InRegClassID && "Unexpected subvector extraction"); |