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| author | Craig Topper <craig.topper@sifive.com> | 2024-01-08 15:23:26 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-08 15:23:26 -0800 |
| commit | faa326de97bf6119dcc42806b07f3523c521ae96 (patch) | |
| tree | fb2423745cdee3f61f7c789d868c63934bbc01dd /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | f5145f4dc819d73ff8bebcfba3779533b150884e (diff) | |
| download | llvm-faa326de97bf6119dcc42806b07f3523c521ae96.zip llvm-faa326de97bf6119dcc42806b07f3523c521ae96.tar.gz llvm-faa326de97bf6119dcc42806b07f3523c521ae96.tar.bz2 | |
[RISCV] Add branch+c.mv macrofusion for sifive-p450. (#76169)
sifive-p450 supports a very restricted version of the short forward
branch optimization from the sifive-7-series.
For sifive-p450, a branch over a single c.mv can be macrofused as a
conditional move operation. Due to encoding restrictions on c.mv, we
can't conditionally move from X0. That would require c.li instead.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 59b2026..bb7a329 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1021,6 +1021,12 @@ def TuneShortForwardBranchOpt def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; +def TuneConditionalCompressedMoveFusion + : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion", + "true", "Enable branch+c.mv fusion">; +def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; +def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; + def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", "SiFive 7-Series processors", [TuneNoDefaultUnroll, |