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author | Philip Reames <preames@rivosinc.com> | 2023-12-01 11:00:59 -0800 |
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committer | GitHub <noreply@github.com> | 2023-12-01 11:00:59 -0800 |
commit | e81796671890b59c110f8e41adc7ca26f8484d20 (patch) | |
tree | 2343ed9003a92b3f60f8e3a5fb6715b697c9329a /llvm/lib/Target/RISCV/RISCVFeatures.td | |
parent | ca2d79f9cad48b7165bf81a7cc24b67f277915f1 (diff) | |
download | llvm-e81796671890b59c110f8e41adc7ca26f8484d20.zip llvm-e81796671890b59c110f8e41adc7ca26f8484d20.tar.gz llvm-e81796671890b59c110f8e41adc7ca26f8484d20.tar.bz2 |
[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)
When we'd originally added unaligned-scalar-mem and
unaligned-vector-mem, they were separated into two parts under the
theory that some processor might implement one, but not the other. At
the moment, we don't have evidence of such a processor. The C/C++ level
interface, and the clang driver command lines have settled on a single
unaligned flag which indicates both scalar and vector support unaligned.
Given that, let's remove the test matrix complexity for a set of
configurations which don't appear useful.
Given these are internal feature names, I don't think we need to provide
any forward compatibility. Anyone disagree?
Note: The immediate trigger for this patch was finding another case
where the unaligned-vector-mem wasn't being properly serialized to IR
from clang which resulted in problems reproducing assembly from clang's
-emit-llvm feature. Instead of fixing this, I decided getting rid of the
complexity was the better approach.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index c5d88ca..7d142d3 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -946,15 +946,10 @@ def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence", "true", "Enable trailing fence for seq-cst store.">; -def FeatureUnalignedScalarMem - : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem", - "true", "Has reasonably performant unaligned scalar " - "loads and stores">; - -def FeatureUnalignedVectorMem - : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem", - "true", "Has reasonably performant unaligned vector " - "loads and stores">; +def FeatureFastUnalignedAccess + : SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess", + "true", "Has reasonably performant unaligned " + "loads and stores (both scalar and vector)">; def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; |