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| author | wangpc <wangpengcheng.pp@bytedance.com> | 2023-12-22 14:20:09 +0800 |
|---|---|---|
| committer | wangpc <wangpengcheng.pp@bytedance.com> | 2023-12-22 14:29:31 +0800 |
| commit | 90f816e61f48c22861aeadf31ca6338f88f9e08a (patch) | |
| tree | dd36b35f4473f683bacd19d549e582ae288f2b7f /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | f25bcfbb291e3d213eaded5cfa84d3d4e7002052 (diff) | |
| download | llvm-90f816e61f48c22861aeadf31ca6338f88f9e08a.zip llvm-90f816e61f48c22861aeadf31ca6338f88f9e08a.tar.gz llvm-90f816e61f48c22861aeadf31ca6338f88f9e08a.tar.bz2 | |
[RISCV] Rename TuneVeyronFusions to TuneVentanaVeyron
And fusion features are added to processor definition.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 2095446..5048e28 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1001,12 +1001,8 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", [TuneNoDefaultUnroll, TuneShortForwardBranchOpt]>; -def TuneVeyronFusions : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", - "Ventana Veyron-Series processors", - [TuneLUIADDIFusion, - TuneAUIPCADDIFusion, - TuneShiftedZExtFusion, - TuneLDADDFusion]>; +def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", + "Ventana Veyron-Series processors">; // Assume that lock-free native-width atomics are available, even if the target // and operating system combination would not usually provide them. The user |