diff options
author | Craig Topper <craig.topper@sifive.com> | 2024-04-16 15:40:32 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-04-16 15:40:32 -0700 |
commit | 9067070d91e9d8cdd8509ffa56a076f08a3d7281 (patch) | |
tree | cebd4d9ab11a03cd6340a183c64b884c7f0a20d3 /llvm/lib/Target/RISCV/RISCVFeatures.td | |
parent | 8aa061ffc75adfab4b3084c918e7d4a3ccd5ba43 (diff) | |
download | llvm-9067070d91e9d8cdd8509ffa56a076f08a3d7281.zip llvm-9067070d91e9d8cdd8509ffa56a076f08a3d7281.tar.gz llvm-9067070d91e9d8cdd8509ffa56a076f08a3d7281.tar.bz2 |
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
This is largely a revert of commit
e81796671890b59c110f8e41adc7ca26f8484d20.
As #88029 shows, there exists hardware that only supports unaligned
scalar.
I'm leaving how this gets exposed to the clang interface to a future
patch.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 5996221..561187c 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1183,10 +1183,15 @@ def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence", "true", "Enable trailing fence for seq-cst store.">; -def FeatureFastUnalignedAccess - : SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess", - "true", "Has reasonably performant unaligned " - "loads and stores (both scalar and vector)">; +def FeatureUnalignedScalarMem + : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem", + "true", "Has reasonably performant unaligned scalar " + "loads and stores">; + +def FeatureUnalignedVectorMem + : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem", + "true", "Has reasonably performant unaligned vector " + "loads and stores">; def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; |