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| author | Luke Lau <luke@igalia.com> | 2024-01-19 06:57:06 +0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-19 06:57:06 +0700 |
| commit | 8649328060b4e748502d1d859f9c9c1bd3c2bccc (patch) | |
| tree | bde341569f031db7a148e7f60e518f0cc6ddde5f /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | 3c5845703c85f221ca12880ce9107a0c44cf7b27 (diff) | |
| download | llvm-8649328060b4e748502d1d859f9c9c1bd3c2bccc.zip llvm-8649328060b4e748502d1d859f9c9c1bd3c2bccc.tar.gz llvm-8649328060b4e748502d1d859f9c9c1bd3c2bccc.tar.bz2 | |
[RISCV] Add support for new unprivileged extensions defined in profiles spec (#77458)
This adds minimal support for 7 new unprivileged extensions that were
defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
* Ziccif: Main memory supports instruction fetch with atomicity
requirement
* Ziccrse: Main memory supports forward progress on LR/SC sequences
* Ziccamoa: Main memory supports all atomics in A
* Zicclsm: Main memory supports misaligned loads/stores
* Za64rs: Reservation set size of 64 bytes
* Za128rs: Reservation set size of 128 bytes
* Zic64b: Cache block size isf 64 bytes
As stated in the specification, these extensions don't add any new
features but
describe existing features. So this patch only adds parsing and
subtarget
features.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index fa334c6..7278093 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -93,6 +93,22 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, AssemblerPredicate<(all_of FeatureStdExtZifencei), "'Zifencei' (fence.i)">; +def FeatureStdExtZiccamoa + : SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true", + "'Ziccamoa' (Main Memory Supports All Atomics in A)">; + +def FeatureStdExtZiccif + : SubtargetFeature<"ziccif", "HasStdExtZiccif", "true", + "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">; + +def FeatureStdExtZicclsm + : SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true", + "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">; + +def FeatureStdExtZiccrse + : SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true", + "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">; + def FeatureStdExtZicntr : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true", "'Zicntr' (Base Counters and Timers)", @@ -517,6 +533,10 @@ def HasStdExtZfhOrZvfh "'Zfh' (Half-Precision Floating-Point) or " "'Zvfh' (Vector Half-Precision Floating-Point)">; +def FeatureStdExtZic64b + : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true", + "'Zic64b' (Cache Block Size Is 64 Bytes)">; + def FeatureStdExtZicbom : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true", "'Zicbom' (Cache-Block Management Instructions)">; @@ -561,6 +581,12 @@ def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, "'Ztso' (Memory Model - Total Store Order)">; def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">; +def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true", + "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">; + +def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true", + "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">; + def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true", "'Zawrs' (Wait on Reservation Set)">; def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">, |