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| author | Yeting Kuo <46629943+yetingk@users.noreply.github.com> | 2023-12-30 15:40:20 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-30 15:40:20 +0800 |
| commit | 3dc0638cfc19e140daff7bf1281648daca8212fa (patch) | |
| tree | 22fb1ca484f500994dcc448d5bd133fa6315bb19 /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | fe2e677aa7aebedd316b1a688db8410855a213c1 (diff) | |
| download | llvm-3dc0638cfc19e140daff7bf1281648daca8212fa.zip llvm-3dc0638cfc19e140daff7bf1281648daca8212fa.tar.gz llvm-3dc0638cfc19e140daff7bf1281648daca8212fa.tar.bz2 | |
[RISCV] Add MC layer support for Zicfiss. (#66043)
The patch adds the instructions in Zicfiss extension. Zicfiss extension
is to support shadow stack for control flow integrity. This patch is
based on version [0.3.1].
[0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index bdab052..59b2026 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -700,6 +700,15 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, AssemblerPredicate<(all_of FeatureStdExtZcmop), "'Zcmop' (Compressed May-Be-Operations)">; +def FeatureStdExtZicfiss + : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true", + "'Zicfiss' (Shadow stack)", + [FeatureStdExtZicsr, FeatureStdExtZimop]>; +def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, + AssemblerPredicate<(all_of FeatureStdExtZicfiss), + "'Zicfiss' (Shadow stack)">; +def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; + def FeatureStdExtSmaia : SubtargetFeature<"smaia", "HasStdExtSmaia", "true", "'Smaia' (Smaia encompasses all added CSRs and all " |