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author | Wang Pengcheng <wangpengcheng.pp@bytedance.com> | 2024-01-16 20:44:30 +0800 |
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committer | GitHub <noreply@github.com> | 2024-01-16 20:44:30 +0800 |
commit | 3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a (patch) | |
tree | 68b2a3710aeeea9c11ef714e5d96f79456cc38e4 /llvm/lib/Target/RISCV/RISCVFeatures.td | |
parent | e2bb47caa69f393b011c2d8e3295587ae35699b5 (diff) | |
download | llvm-3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a.zip llvm-3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a.tar.gz llvm-3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a.tar.bz2 |
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
This commit includes the necessary changes to clang and LLVM to support
codegen of `RVE` and the `ilp32e`/`lp64e` ABIs.
The differences between `RVE` and `RVI` are:
* `RVE` reduces the integer register count to 16(x0-x16).
* The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits.
`RVE` can be combined with all current standard extensions.
The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are:
* Only 6 integer argument registers (rather than 8).
* Only 2 callee-saved registers (rather than 12).
* A Stack Alignment of 32bits (rather than 128bits).
* ilp32e isn't compatible with D ISA extension.
If `ilp32e` or `lp64` is used with an ISA that has any of the registers
x16-x31 and f0-f31, then these registers are considered temporaries.
To be compatible with the implementation of ilp32e in GCC, we don't use
aligned registers to pass variadic arguments and set stack alignment\
to 4-bytes for types with length of 2*XLEN.
FastCC is also supported on RVE, while GHC isn't since there is only one
avaiable register.
Differential Revision: https://reviews.llvm.org/D70401
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index f4af08fc..fa334c6 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -17,6 +17,13 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, AssemblerPredicate<(all_of FeatureStdExtZicsr), "'Zicsr' (CSRs)">; +def FeatureStdExtI + : SubtargetFeature<"i", "HasStdExtI", "true", + "'I' (Base Integer Instruction Set)">; +def HasStdExtI : Predicate<"Subtarget->hasStdExtI()">, + AssemblerPredicate<(all_of FeatureStdExtI), + "'I' (Base Integer Instruction Set)">; + def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true", "'M' (Integer Multiplication and Division)">; |