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| author | Craig Topper <craig.topper@sifive.com> | 2024-01-11 23:53:00 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-11 23:53:00 -0800 |
| commit | 2e78c220fc18bc79cf396b96c65de6d4446318c6 (patch) | |
| tree | 4982de719ee85fdc8e805ec80881f913a41d0532 /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | 7e604485e18d40be6ce6310e4a3e583ca0b7df47 (diff) | |
| download | llvm-2e78c220fc18bc79cf396b96c65de6d4446318c6.zip llvm-2e78c220fc18bc79cf396b96c65de6d4446318c6.tar.gz llvm-2e78c220fc18bc79cf396b96c65de6d4446318c6.tar.bz2 | |
[RISCV] Simplify the description for ssaia and smaia. (#77870)
It feels more important to expand out Advanced Interrupt Architecture
for users than to have a description that explains how one extension is
different from the other.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 4c99d8c..72b9c2c 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -711,16 +711,13 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; def FeatureStdExtSmaia : SubtargetFeature<"smaia", "HasStdExtSmaia", "true", - "'Smaia' (Smaia encompasses all added CSRs and all " - "modifications to interrupt response behavior that the " - "AIA specifies for a hart, over all privilege levels.)", - []>; + "'Smaia' (Advanced Interrupt Architecture Machine " + "Level)", []>; def FeatureStdExtSsaia : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true", - "'Ssaia' (Ssaia is essentially the same as Smaia except " - "excluding the machine-level CSRs and behavior not " - "directly visible to supervisor level.)", []>; + "'Ssaia' (Advanced Interrupt Architecture Supervisor " + "Level)", []>; def HasHalfFPLoadStoreMove : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">, |