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| author | Mikhail Gudim <mgudim@gmail.com> | 2023-12-11 16:34:13 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-11 16:34:13 -0500 |
| commit | 29ee66f4a0967e43a035f147c960743c7b640f2f (patch) | |
| tree | 5b820a2565cb43aef86aeb99fe88b31d41a40acb /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | 86fa4b2c46191fe6be88e38bb46487472f6892c9 (diff) | |
| download | llvm-29ee66f4a0967e43a035f147c960743c7b640f2f.zip llvm-29ee66f4a0967e43a035f147c960743c7b640f2f.tar.gz llvm-29ee66f4a0967e43a035f147c960743c7b640f2f.tar.bz2 | |
[RISCV] Macro-fusion support for veyron-v1 CPU. (#70012)
Support was added for the following fusions:
auipc-addi, slli-srli, ld-add
Some parts of the code became repetative, so small refactoring of
existing lui-addi fusion was done.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 7d142d3..294927a 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -970,6 +970,16 @@ def TuneLUIADDIFusion : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion", "true", "Enable LUI+ADDI macrofusion">; +def TuneAUIPCADDIFusion + : SubtargetFeature<"auipc-addi-fusion", "HasAUIPCADDIFusion", + "true", "Enable AUIPC+ADDI macrofusion">; +def TuneShiftedZExtFusion + : SubtargetFeature<"shifted-zext-fusion", "HasShiftedZExtFusion", + "true", "Enable SLLI+SRLI to be fused when computing (shifted) zero extension">; +def TuneLDADDFusion + : SubtargetFeature<"ld-add-fusion", "HasLDADDFusion", + "true", "Enable LD+ADD macrofusion.">; + def TuneNoDefaultUnroll : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false", "Disable default unroll preference.">; @@ -987,9 +997,12 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", [TuneNoDefaultUnroll, TuneShortForwardBranchOpt]>; -def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", - "Ventana-Veyron Series processors", - [TuneLUIADDIFusion]>; +def TuneVeyronFusions : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", + "Ventana Veyron-Series processors", + [TuneLUIADDIFusion, + TuneAUIPCADDIFusion, + TuneShiftedZExtFusion, + TuneLDADDFusion]>; // Assume that lock-free native-width atomics are available, even if the target // and operating system combination would not usually provide them. The user |