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| author | Craig Topper <craig.topper@sifive.com> | 2024-01-10 12:00:40 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-10 12:00:40 -0800 |
| commit | 0a1b066bbaf7e3800f47697231d7e1e91744ecbf (patch) | |
| tree | b41f95501f08193ccabba9511443de76f5c03a7b /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | 2dde029df8f9e3b2ece6899dc73bea226f227d11 (diff) | |
| download | llvm-0a1b066bbaf7e3800f47697231d7e1e91744ecbf.zip llvm-0a1b066bbaf7e3800f47697231d7e1e91744ecbf.tar.gz llvm-0a1b066bbaf7e3800f47697231d7e1e91744ecbf.tar.bz2 | |
[RISCV] Support isel for Zacas for XLen and i32. (#77666)
This adds new isel patterns for Zacas that take priority over the
pseudoinstructions we use for the A extension.
Support for 2x XLen types will come in a separate patch since they need
to be done differently.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index bb7a329..2795095 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -736,6 +736,7 @@ def FeatureStdExtZacas def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, AssemblerPredicate<(all_of FeatureStdExtZacas), "'Zacas' (Atomic Compare-And-Swap Instructions)">; +def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; //===----------------------------------------------------------------------===// // Vendor extensions |