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| author | Alexey Bataev <a.bataev@outlook.com> | 2024-02-29 15:49:05 +0000 |
|---|---|---|
| committer | Alexey Bataev <a.bataev@outlook.com> | 2024-02-29 15:49:05 +0000 |
| commit | a0d744b9cf4a5bd7219c5c1007d8db317b70cf1f (patch) | |
| tree | 40d806f565e8f0ebdafb78f01db92fe4499096f9 /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | 46478028cda679b76757cae689a53b11fadad5f5 (diff) | |
| parent | 4f132dca711f4b425f9d370f5d59efb766b8bffa (diff) | |
| download | llvm-users/alexey-bataev/spr/ttiriscvimprove-costs-for-fixed-vector-whole-reg-extractinsert.zip llvm-users/alexey-bataev/spr/ttiriscvimprove-costs-for-fixed-vector-whole-reg-extractinsert.tar.gz llvm-users/alexey-bataev/spr/ttiriscvimprove-costs-for-fixed-vector-whole-reg-extractinsert.tar.bz2 | |
Rebase, Address commentsusers/alexey-bataev/spr/ttiriscvimprove-costs-for-fixed-vector-whole-reg-extractinsert
Created using spr 1.3.5
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index bcaf447..9773b29 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -185,7 +185,7 @@ def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">, "'Zabha' (Byte and Halfword Atomic Memory Operations)">; def FeatureStdExtZacas - : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true", + : SubtargetFeature<"zacas", "HasStdExtZacas", "true", "'Zacas' (Atomic Compare-And-Swap Instructions)">; def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, AssemblerPredicate<(all_of FeatureStdExtZacas), |