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authorHal Finkel <hfinkel@anl.gov>2013-03-15 05:06:04 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-15 05:06:04 +0000
commitbb420f10e98e1ce469d1e767fee797bb9b5ef2c1 (patch)
tree951ae6dbb88da4d63926b2eb8a1cfc88f880587b /llvm/lib/Target/PowerPC/PPCFrameLowering.h
parentcb7733c33c8bd2c24f43967447f6e739fb768c7b (diff)
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Allocate the RS spill slot for any PPC function with spills and a large stack frame
For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. llvm-svn: 177140
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCFrameLowering.h')
-rw-r--r--llvm/lib/Target/PowerPC/PPCFrameLowering.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.h b/llvm/lib/Target/PowerPC/PPCFrameLowering.h
index 8d9d395..53ee326 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.h
@@ -32,7 +32,9 @@ public:
Subtarget(sti) {
}
- void determineFrameLayout(MachineFunction &MF) const;
+ unsigned determineFrameLayout(MachineFunction &MF,
+ bool UpdateMF = true,
+ bool UseEstimate = false) const;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
@@ -46,6 +48,7 @@ public:
RegScavenger *RS = NULL) const;
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = NULL) const;
+ void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,