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| author | Austin Kerbow <Austin.Kerbow@amd.com> | 2023-08-01 17:51:59 -0700 |
|---|---|---|
| committer | Austin Kerbow <Austin.Kerbow@amd.com> | 2023-09-19 15:45:16 -0700 |
| commit | 69447d6afe702dee6bc1dbe17f4915789ad6889d (patch) | |
| tree | 153c0e88aec453d1acf9eb354b03db85f09cbb04 /llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | |
| parent | 30d77fb80857e645b300c8f59cad9414d090e083 (diff) | |
| download | llvm-69447d6afe702dee6bc1dbe17f4915789ad6889d.zip llvm-69447d6afe702dee6bc1dbe17f4915789ad6889d.tar.gz llvm-69447d6afe702dee6bc1dbe17f4915789ad6889d.tar.bz2 | |
[AMDGPU] Add ASM and MC updates for preloading kernargs
Add assembler directives for preloading kernel arguments that correspond
to new fields in the kernel descriptor for the length and offset of
arguments that will be placed in SGPRs prior to kernel launch. Alignment
of the arguments in SGPRs is equivalent to the kernarg segment when
accessed via the kernarg_segment_ptr. Kernarg SGPRs are allocated
directly after other user SGPRs.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D159459
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index 2273ba9..5b0a72b 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -1148,6 +1148,7 @@ bool hasG16(const MCSubtargetInfo &STI); bool hasPackedD16(const MCSubtargetInfo &STI); bool hasGDS(const MCSubtargetInfo &STI); unsigned getNSAMaxSize(const MCSubtargetInfo &STI); +unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI); bool isSI(const MCSubtargetInfo &STI); bool isCI(const MCSubtargetInfo &STI); @@ -1174,6 +1175,7 @@ bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI); bool hasMAIInsts(const MCSubtargetInfo &STI); bool hasVOPD(const MCSubtargetInfo &STI); int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR); +unsigned hasKernargPreload(const MCSubtargetInfo &STI); /// Is Reg - scalar register bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI); |