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author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2022-11-24 13:47:01 +0530 |
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committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2022-12-17 11:55:34 +0530 |
commit | b5efec4b27bf5451a4fae74973f7a7a28fbc6108 (patch) | |
tree | f4113b0cf51583fc334f5bd7d0d382f8b81f6d82 /llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | |
parent | ce02d5a5395632519f067409c42943bfd9aa2294 (diff) | |
download | llvm-b5efec4b27bf5451a4fae74973f7a7a28fbc6108.zip llvm-b5efec4b27bf5451a4fae74973f7a7a28fbc6108.tar.gz llvm-b5efec4b27bf5451a4fae74973f7a7a28fbc6108.tar.bz2 |
[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot
With D134950, targets get notified when a virtual register is created and/or
cloned. Targets can do the needful with the delegate callback. AMDGPU propagates
the virtual register flags maintained in the target file itself. They are useful
to identify a certain type of machine operands while inserting spill stores and
reloads. Since RegAllocFast spills the physical register itself, there is no way
its virtual register can be mapped back to retrieve the flags. It can be solved
by passing the virtual register as an additional argument. This argument has no
use when the spill interfaces are called during the greedy allocator or even the
PrologEpilogInserter and can pass a null register in such cases.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D138656
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 05eba7c..3450a9f 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -102,7 +102,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock, // range. const bool IsLiveIn = MRI.isLiveIn(Reg); TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(), - RC, TRI); + RC, TRI, Register()); if (Indexes) { assert(std::distance(MIS.begin(), I) == 1); @@ -137,7 +137,8 @@ static void insertCSRRestores(MachineBasicBlock &RestoreBlock, const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32); - TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, TRI); + TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, TRI, + Register()); assert(I != RestoreBlock.begin() && "loadRegFromStackSlot didn't insert any code!"); // Insert in reverse order. loadRegFromStackSlot can insert |