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| author | Sander de Smalen <sander.desmalen@arm.com> | 2024-06-19 14:24:28 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-19 14:24:28 +0100 |
| commit | 93831c73ea51dcf4dc1832a4ea5616b819d36f31 (patch) | |
| tree | 1e013706e948a94e833d2441a57dabc940088995 /llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | |
| parent | 0d524bc45ddaa2bd94c28c8935e53153827f2374 (diff) | |
| download | llvm-93831c73ea51dcf4dc1832a4ea5616b819d36f31.zip llvm-93831c73ea51dcf4dc1832a4ea5616b819d36f31.tar.gz llvm-93831c73ea51dcf4dc1832a4ea5616b819d36f31.tar.bz2 | |
[AArch64] Let patterns for NEON instructions check runtime mode. (#95560)
This helps identify any failures where the compiler might otherwise
silently emit instructions that are not valid for the given runtime mode.
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 9f6f66e..0f0606c 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -22368,7 +22368,8 @@ static SDValue vectorToScalarBitmask(SDNode *N, SelectionDAG &DAG) { ComparisonResult = DAG.getSExtOrTrunc(ComparisonResult, DL, VecVT); SmallVector<SDValue, 16> MaskConstants; - if (VecVT == MVT::v16i8) { + if (DAG.getSubtarget<AArch64Subtarget>().isNeonAvailable() && + VecVT == MVT::v16i8) { // v16i8 is a special case, as we have 16 entries but only 8 positional bits // per entry. We split it into two halves, apply the mask, zip the halves to // create 8x 16-bit values, and the perform the vector reduce. |