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| author | Sacha Coppey <sacha.coppey@oracle.com> | 2023-11-17 16:01:00 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2023-11-17 16:30:09 +0000 |
| commit | aeedc0763772b398a725ab34d8a9cc1d698c60cb (patch) | |
| tree | 0ca52a6ad3143fa8858b5ae15f05ae29aa408a77 /llvm/lib/IR | |
| parent | 19e745890b8658825de63ce4d839537c7707e425 (diff) | |
| download | llvm-aeedc0763772b398a725ab34d8a9cc1d698c60cb.zip llvm-aeedc0763772b398a725ab34d8a9cc1d698c60cb.tar.gz llvm-aeedc0763772b398a725ab34d8a9cc1d698c60cb.tar.bz2 | |
[IR] Add GraalVM calling conventions
Adds GraalVM calling conventions. The only difference with the default calling conventions is that GraalVM reserves two registers for the heap base and the thread. Since the registers are then accessed by name, getRegisterByName has to be updated accordingly.
This patch implements the calling conventions only for X86, AArch64 and RISC-V.
For X86, the reserved registers are X14 and X15. For AArch64, they are X27 and X28. For RISC-V, they are X23 and X27.
This patch has been used by the LLVM backend of GraalVM's Native Image project in production for around 4 months with no major issues.
Differential Revision: https://reviews.llvm.org/D151107
Diffstat (limited to 'llvm/lib/IR')
| -rw-r--r-- | llvm/lib/IR/AsmWriter.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index a7d667d..c37adb4 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -307,6 +307,7 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) { case CallingConv::CXX_FAST_TLS: Out << "cxx_fast_tlscc"; break; case CallingConv::GHC: Out << "ghccc"; break; case CallingConv::Tail: Out << "tailcc"; break; + case CallingConv::GRAAL: Out << "graalcc"; break; case CallingConv::CFGuard_Check: Out << "cfguard_checkcc"; break; case CallingConv::X86_StdCall: Out << "x86_stdcallcc"; break; case CallingConv::X86_FastCall: Out << "x86_fastcallcc"; break; |