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authorPhoebe Wang <phoebe.wang@intel.com>2022-12-13 22:28:47 +0800
committerPhoebe Wang <phoebe.wang@intel.com>2022-12-13 22:30:31 +0800
commit7168e501e4ee9cafecdcfd7c7216909f4609f88a (patch)
tree541bf25ca15d79115eec898e2c5c11a9fafa16c4 /llvm/lib/CodeGen
parentae2e60a814f212e246c5009641fcdcf536fc8d0c (diff)
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[NFC] Add checks for potential null returns
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/BreakFalseDeps.cpp1
-rw-r--r--llvm/lib/CodeGen/SelectOptimize.cpp2
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp1
3 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 57170c5..3102731 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -135,6 +135,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
// Get the undef operand's register class
const TargetRegisterClass *OpRC =
TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);
+ assert(OpRC && "Not a valid register class");
// If the instruction has a true dependency, we can hide the false depdency
// behind it.
diff --git a/llvm/lib/CodeGen/SelectOptimize.cpp b/llvm/lib/CodeGen/SelectOptimize.cpp
index 5d4d982..d335aca 100644
--- a/llvm/lib/CodeGen/SelectOptimize.cpp
+++ b/llvm/lib/CodeGen/SelectOptimize.cpp
@@ -932,7 +932,7 @@ bool SelectOptimize::computeLoopCosts(
// PredictedPathCost = TrueOpCost * TrueProb + FalseOpCost * FalseProb
// MispredictCost = max(MispredictPenalty, CondCost) * MispredictRate
if (SIset.contains(&I)) {
- auto SI = dyn_cast<SelectInst>(&I);
+ auto SI = cast<SelectInst>(&I);
Scaled64 TrueOpCost = Scaled64::getZero(),
FalseOpCost = Scaled64::getZero();
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 6b12e9d..0be11b6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -340,6 +340,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
unsigned Idx = RegDefPos.GetIdx();
const MCInstrDesc Desc = TII->get(Opcode);
const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
+ assert(RC && "Not a valid register class");
RegClass = RC->getID();
// FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
// better way to determine it.