diff options
author | Benjamin Maxwell <benjamin.maxwell@arm.com> | 2022-12-12 16:26:20 +0000 |
---|---|---|
committer | Benjamin Maxwell <benjamin.maxwell@arm.com> | 2022-12-15 13:50:02 +0000 |
commit | 3010f60381bcd828d1b409cfaa576328bcd05bbc (patch) | |
tree | 3bdc07cd8549b5699cff8cabb023c331ea0a4645 /llvm/lib/CodeGen | |
parent | 1cdffa359a3344f966ed309de17af17f8abfbe4d (diff) | |
download | llvm-3010f60381bcd828d1b409cfaa576328bcd05bbc.zip llvm-3010f60381bcd828d1b409cfaa576328bcd05bbc.tar.gz llvm-3010f60381bcd828d1b409cfaa576328bcd05bbc.tar.bz2 |
Reland "[TargetLowering] Teach DemandedBits about VSCALE"
Reland with a fixup to avoid converting APInts to int64_t which allowed for
overflows (UB) with sufficiently high/low multiplier values.
This allows DemandedBits to see the result of VSCALE will be at most
VScaleMax * some compile-time constant. This relies on the vscale_range()
attribute being present on the function, with a max set. (This is done by
default when clang is targeting AArch64+SVE).
Using this various redundant operations (zexts, sexts, ands, ors, etc)
can be eliminated.
Differential Revision: https://reviews.llvm.org/D138508
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 202178e..a0e7705 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1125,6 +1125,23 @@ bool TargetLowering::SimplifyDemandedBits( KnownBits Known2; switch (Op.getOpcode()) { + case ISD::VSCALE: { + Function const &F = TLO.DAG.getMachineFunction().getFunction(); + Attribute const &Attr = F.getFnAttribute(Attribute::VScaleRange); + if (!Attr.isValid()) + return false; + std::optional<unsigned> MaxVScale = Attr.getVScaleRangeMax(); + if (!MaxVScale.has_value()) + return false; + APInt VScaleResultUpperbound = *MaxVScale * Op.getConstantOperandAPInt(0); + bool Negative = VScaleResultUpperbound.isNegative(); + if (Negative) + VScaleResultUpperbound = ~VScaleResultUpperbound; + unsigned RequiredBits = VScaleResultUpperbound.getActiveBits(); + if (RequiredBits < BitWidth) + (Negative ? Known.One : Known.Zero).setHighBits(BitWidth - RequiredBits); + return false; + } case ISD::SCALAR_TO_VECTOR: { if (VT.isScalableVector()) return false; |