diff options
author | Justin Bogner <mail@justinbogner.com> | 2017-10-10 23:50:49 +0000 |
---|---|---|
committer | Justin Bogner <mail@justinbogner.com> | 2017-10-10 23:50:49 +0000 |
commit | fdf9bf4f16739daa62fa8d9177b1c3a8346728ae (patch) | |
tree | 8184e1ecc06220f23157214474c5ae63e04a1050 /llvm/lib/CodeGen/RegisterScavenging.cpp | |
parent | 0bf7717a02cd483e0272c30195da1740efcae9ed (diff) | |
download | llvm-fdf9bf4f16739daa62fa8d9177b1c3a8346728ae.zip llvm-fdf9bf4f16739daa62fa8d9177b1c3a8346728ae.tar.gz llvm-fdf9bf4f16739daa62fa8d9177b1c3a8346728ae.tar.bz2 |
CodeGen: Minor cleanups to use MachineInstr::getMF. NFC
Since r315388 we have a shorter way to say this, so we'll replace
MI->getParent()->getParent() with MI->getMF() in a few places.
llvm-svn: 315390
Diffstat (limited to 'llvm/lib/CodeGen/RegisterScavenging.cpp')
-rw-r--r-- | llvm/lib/CodeGen/RegisterScavenging.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index fdd10ed..844ddb9 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -463,7 +463,7 @@ RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj, MachineBasicBlock::iterator &UseMI) { // Find an available scavenging slot with size and alignment matching // the requirements of the class RC. - const MachineFunction &MF = *Before->getParent()->getParent(); + const MachineFunction &MF = *Before->getMF(); const MachineFrameInfo &MFI = MF.getFrameInfo(); unsigned NeedSize = TRI->getSpillSize(RC); unsigned NeedAlign = TRI->getSpillAlignment(RC); @@ -536,7 +536,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj) { MachineInstr &MI = *I; - const MachineFunction &MF = *MI.getParent()->getParent(); + const MachineFunction &MF = *MI.getMF(); // Consider all allocatable registers in the register class initially BitVector Candidates = TRI->getAllocatableSet(MF, RC); |