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| author | Oliver Stannard <oliver.stannard@linaro.org> | 2019-08-02 10:23:17 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@linaro.org> | 2019-08-02 10:23:17 +0000 |
| commit | 4b7239ebaca72f2cd92682019fbe0bef5b46cd4e (patch) | |
| tree | 9e69d9d57dd2290f21ab73a63cf156a676e4cf36 /llvm/lib/CodeGen/RegUsageInfoCollector.cpp | |
| parent | f6b00c279a5587a25876752a6ecd8da0bed959dc (diff) | |
| download | llvm-4b7239ebaca72f2cd92682019fbe0bef5b46cd4e.zip llvm-4b7239ebaca72f2cd92682019fbe0bef5b46cd4e.tar.gz llvm-4b7239ebaca72f2cd92682019fbe0bef5b46cd4e.tar.bz2 | |
[IPRA][ARM] Disable no-CSR optimisation for ARM
This optimisation isn't generally profitable for ARM, because we can
save/restore many registers in the prologue and epilogue using the PUSH
and POP instructions, but mostly use individual LDR/STR instructions for
other spills.
Differential revision: https://reviews.llvm.org/D64910
llvm-svn: 367670
Diffstat (limited to 'llvm/lib/CodeGen/RegUsageInfoCollector.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegUsageInfoCollector.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp index 64552b5..757ff0e 100644 --- a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp @@ -171,7 +171,8 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { SetRegAsDefined(PReg); } - if (TargetFrameLowering::isSafeForNoCSROpt(F)) { + if (TargetFrameLowering::isSafeForNoCSROpt(F) && + MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) { ++NumCSROpt; LLVM_DEBUG(dbgs() << MF.getName() << " function optimized for not having CSR.\n"); |