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author | Dan Gohman <gohman@apple.com> | 2009-10-13 23:58:05 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-10-13 23:58:05 +0000 |
commit | 0aa63c97cea4cbaa486c50a65bd2ebdaa9f5bf4e (patch) | |
tree | 78c98e074a353ffe03e6b89b63c92b31e8169135 /llvm/lib/CodeGen/README.txt | |
parent | 3362bde8ecca25774fa3c018acbbc3a0f4a94477 (diff) | |
download | llvm-0aa63c97cea4cbaa486c50a65bd2ebdaa9f5bf4e.zip llvm-0aa63c97cea4cbaa486c50a65bd2ebdaa9f5bf4e.tar.gz llvm-0aa63c97cea4cbaa486c50a65bd2ebdaa9f5bf4e.tar.bz2 |
Add a few README.txt items.
llvm-svn: 84059
Diffstat (limited to 'llvm/lib/CodeGen/README.txt')
-rw-r--r-- | llvm/lib/CodeGen/README.txt | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/README.txt b/llvm/lib/CodeGen/README.txt index 64374ce..8e9ead7 100644 --- a/llvm/lib/CodeGen/README.txt +++ b/llvm/lib/CodeGen/README.txt @@ -206,3 +206,32 @@ Stack coloring improvments: not spill slots. 2. Reorder objects to fill in gaps between objects. e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4 + +//===---------------------------------------------------------------------===// + +The scheduler should be able to sort nearby instructions by their address. For +example, in an expanded memset sequence it's not uncommon to see code like this: + + movl $0, 4(%rdi) + movl $0, 8(%rdi) + movl $0, 12(%rdi) + movl $0, 0(%rdi) + +Each of the stores is independent, and the scheduler is currently making an +arbitrary decision about the order. + +//===---------------------------------------------------------------------===// + +Another opportunitiy in this code is that the $0 could be moved to a register: + + movl $0, 4(%rdi) + movl $0, 8(%rdi) + movl $0, 12(%rdi) + movl $0, 0(%rdi) + +This would save substantial code size, especially for longer sequences like +this. It would be easy to have a rule telling isel to avoid matching MOV32mi +if the immediate has more than some fixed number of uses. It's more involved +to teach the register allocator how to do late folding to recover from +excessive register pressure. + |