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author | Jay Foad <jay.foad@amd.com> | 2023-05-24 14:57:23 +0100 |
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committer | Jay Foad <jay.foad@amd.com> | 2023-06-01 19:17:34 +0100 |
commit | 5022fc2ad31b5e3211e2458347c89412b8c5ec1b (patch) | |
tree | 3ce4e7d2001a8552c457ae8a0ec1b58fc669f4ae /llvm/lib/CodeGen/MachineSink.cpp | |
parent | 2de54b919ba5fd9ccf37038cddfc36e97eb480af (diff) | |
download | llvm-5022fc2ad31b5e3211e2458347c89412b8c5ec1b.zip llvm-5022fc2ad31b5e3211e2458347c89412b8c5ec1b.tar.gz llvm-5022fc2ad31b5e3211e2458347c89412b8c5ec1b.tar.bz2 |
[CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.
Differential Revision: https://reviews.llvm.org/D151424
Diffstat (limited to 'llvm/lib/CodeGen/MachineSink.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineSink.cpp | 27 |
1 files changed, 9 insertions, 18 deletions
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 1bd3705..e18a19e 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -602,9 +602,7 @@ bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr &MI, // MI is cheap, we probably don't want to break the critical edge for it. // However, if this would allow some definitions of its source operands // to be sunk then it's probably worth it. - for (const MachineOperand &MO : MI.operands()) { - if (!MO.isReg() || !MO.isUse()) - continue; + for (const MachineOperand &MO : MI.all_uses()) { Register Reg = MO.getReg(); if (Reg == 0) continue; @@ -1381,9 +1379,7 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore, // If the instruction to move defines a dead physical register which is live // when leaving the basic block, don't move it because it could turn into a // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>) - for (const MachineOperand &MO : MI.operands()) { - if (!MO.isReg() || MO.isUse()) - continue; + for (const MachineOperand &MO : MI.all_defs()) { Register Reg = MO.getReg(); if (Reg == 0 || !Reg.isPhysical()) continue; @@ -1461,8 +1457,8 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore, // Collect debug users of any vreg that this inst defines. SmallVector<MIRegs, 4> DbgUsersToSink; - for (auto &MO : MI.operands()) { - if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual()) + for (auto &MO : MI.all_defs()) { + if (!MO.getReg().isVirtual()) continue; if (!SeenDbgUsers.count(MO.getReg())) continue; @@ -1496,10 +1492,8 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore, // Note that we have to clear the kill flags for any register this instruction // uses as we may sink over another instruction which currently kills the // used registers. - for (MachineOperand &MO : MI.operands()) { - if (MO.isReg() && MO.isUse()) - RegsToClearKillFlags.insert(MO.getReg()); // Remember to clear kill flags. - } + for (MachineOperand &MO : MI.all_uses()) + RegsToClearKillFlags.insert(MO.getReg()); // Remember to clear kill flags. return true; } @@ -1515,8 +1509,8 @@ void MachineSinking::SalvageUnsunkDebugUsersOfCopy( SmallVector<MachineInstr *, 4> DbgDefUsers; SmallVector<Register, 4> DbgUseRegs; const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); - for (auto &MO : MI.operands()) { - if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual()) + for (auto &MO : MI.all_defs()) { + if (!MO.getReg().isVirtual()) continue; DbgUseRegs.push_back(MO.getReg()); for (auto &User : MRI.use_instructions(MO.getReg())) { @@ -1842,10 +1836,7 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB, // recorded which reg units that DBG_VALUEs read, if this instruction // writes any of those units then the corresponding DBG_VALUEs must sink. MapVector<MachineInstr *, MIRegs::second_type> DbgValsToSinkMap; - for (auto &MO : MI.operands()) { - if (!MO.isReg() || !MO.isDef()) - continue; - + for (auto &MO : MI.all_defs()) { for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid(); ++RI) { for (const auto &MIRegs : SeenDbgInstrs.lookup(*RI)) { auto &Regs = DbgValsToSinkMap[MIRegs.first]; |