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author | Jay Foad <jay.foad@amd.com> | 2023-04-17 11:06:06 +0100 |
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committer | Jay Foad <jay.foad@amd.com> | 2023-04-27 09:40:06 +0100 |
commit | 47d3cbcf842a036c20c3f1c74255cdfc213f41c2 (patch) | |
tree | 7954d0895359047d2b4e4ee369941f2610227169 /llvm/lib/CodeGen/BranchFolding.cpp | |
parent | 12b70ad68ccf3e9415cb6c42f8eb73e883f159ae (diff) | |
download | llvm-47d3cbcf842a036c20c3f1c74255cdfc213f41c2.zip llvm-47d3cbcf842a036c20c3f1c74255cdfc213f41c2.tar.gz llvm-47d3cbcf842a036c20c3f1c74255cdfc213f41c2.tar.bz2 |
[BranchFolder] Skip redundant IMPLICIT_DEFs of subregs
Differential Revision: https://reviews.llvm.org/D148509
Diffstat (limited to 'llvm/lib/CodeGen/BranchFolding.cpp')
-rw-r--r-- | llvm/lib/CodeGen/BranchFolding.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp index 1b78f50..a5302a6 100644 --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -860,6 +860,14 @@ void BranchFolder::mergeCommonTails(unsigned commonTailIndex) { for (Register Reg : NewLiveIns) { if (!LiveRegs.available(*MRI, Reg)) continue; + + // Skip the register if we are about to add one of its super registers. + // TODO: Common this up with the same logic in addLineIns(). + if (any_of(TRI->superregs(Reg), [&](MCPhysReg SReg) { + return NewLiveIns.contains(SReg) && !MRI->isReserved(SReg); + })) + continue; + DebugLoc DL; BuildMI(*Pred, InsertBefore, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Reg); |