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| author | bjacob <jacob.benoit.1@gmail.com> | 2023-10-17 10:47:33 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-17 10:47:33 -0400 |
| commit | 3dc263b18c082c380c559e88f6d4cb6ce54a2e53 (patch) | |
| tree | e7616d3b9bf09e4674f5adc4a1dbe1fac6399292 /llvm/docs/LangRef.rst | |
| parent | c38598186bbc442882610ee15ca4fd9ec022c9c8 (diff) | |
| download | llvm-3dc263b18c082c380c559e88f6d4cb6ce54a2e53.zip llvm-3dc263b18c082c380c559e88f6d4cb6ce54a2e53.tar.gz llvm-3dc263b18c082c380c559e88f6d4cb6ce54a2e53.tar.bz2 | |
Update documentation on x86 constraint codes (#68830)
This updates the documentation on these inline asm constraint codes to
match reality. Context:
https://github.com/llvm/llvm-project/issues/68818#issuecomment-1758180020
Note: dropping also the `'o'` from the docs because I can't find any
mention of it in X86ISelLowering.cpp.
Diffstat (limited to 'llvm/docs/LangRef.rst')
| -rw-r--r-- | llvm/docs/LangRef.rst | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index ee893d8..40eee1f 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -5282,7 +5282,6 @@ X86: - ``O``: An immediate integer between 0 and 127. - ``e``: An immediate 32-bit signed integer. - ``Z``: An immediate 32-bit unsigned integer. -- ``o``, ``v``: Treated the same as ``m``, at the moment. - ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit ``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d`` registers, and on X86-64, it is all of the integer registers. @@ -5293,10 +5292,13 @@ X86: existed since i386, and can be accessed without the REX prefix. - ``f``: A 32, 64, or 80-bit '387 FPU stack pseudo-register. - ``y``: A 64-bit MMX register, if MMX is enabled. -- ``x``: If SSE is enabled: a 32 or 64-bit scalar operand, or 128-bit vector +- ``v``: If SSE is enabled: a 32 or 64-bit scalar operand, or 128-bit vector operand in a SSE register. If AVX is also enabled, can also be a 256-bit vector operand in an AVX register. If AVX-512 is also enabled, can also be a - 512-bit vector operand in an AVX512 register, Otherwise, an error. + 512-bit vector operand in an AVX512 register. Otherwise, an error. +- ``x``: The same as ``v``, except that when AVX-512 is enabled, the ``x`` code + only allocates into the first 16 AVX-512 registers, while the ``v`` code + allocates into any of the 32 AVX-512 registers. - ``Y``: The same as ``x``, if *SSE2* is enabled, otherwise an error. - ``A``: Special case: allocates EAX first, then EDX, for a single operand (in 32-bit mode, a 64-bit integer operand will get split into two registers). It |