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| author | Jason Molenda <jmolenda@apple.com> | 2023-08-15 13:19:07 -0700 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 2023-08-15 13:21:33 -0700 |
| commit | 3ad618f4aea1ef7442f7ff75d92632aec177a4fd (patch) | |
| tree | d98cd63991a5a484a70a3c270c215765bfb48a2d /lldb/docs | |
| parent | fa6726e27bb872ada13fe44c6609e9336785dd36 (diff) | |
| download | llvm-3ad618f4aea1ef7442f7ff75d92632aec177a4fd.zip llvm-3ad618f4aea1ef7442f7ff75d92632aec177a4fd.tar.gz llvm-3ad618f4aea1ef7442f7ff75d92632aec177a4fd.tar.bz2 | |
Update qHostInfo/LC_NOTE so multiple address bits can be specified
On AArch64 systems, we may have different page table setups for
low memory and high memory, and therefore a different number of
bits used for addressing depending on which half of memory the
address is in.
This patch extends the qHostInfo and LC_NOTE "addrable bits" so
that it can specify the number of addressing bits in high memory
and in low memory separately. It builds on the patch I added in
https://reviews.llvm.org/D151292 where Process tracks the separate
address masks, and there is a user setting to set them manually.
Differential Revision: https://reviews.llvm.org/D157667
rdar://113225907
Diffstat (limited to 'lldb/docs')
| -rw-r--r-- | lldb/docs/lldb-gdb-remote.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lldb/docs/lldb-gdb-remote.txt b/lldb/docs/lldb-gdb-remote.txt index 27adaa3..bfc1013 100644 --- a/lldb/docs/lldb-gdb-remote.txt +++ b/lldb/docs/lldb-gdb-remote.txt @@ -978,6 +978,14 @@ addressing_bits: optional, specifies how many bits in addresses are v8.3 ABIs that use pointer authentication, so lldb knows which bits to clear/set to get the actual addresses. +low_mem_addressing_bits: optional, specifies how many bits in + addresses in low memory are significant for addressing, base 10. + AArch64 can have different page table setups for low and high + memory, and therefore a different number of bits used for addressing. +high_mem_addressing_bits: optional, specifies how many bits in + addresses in high memory are significant for addressing, base 10. + AArch64 can have different page table setups for low and high + memory, and therefore a different number of bits used for addressing. //---------------------------------------------------------------------- // "qGDBServerVersion" |