diff options
| author | Simon Tatham <simon.tatham@arm.com> | 2022-07-26 09:20:46 +0100 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2022-07-26 09:35:30 +0100 |
| commit | 2b38f589301d7defef6099b57ecf45139010a5a7 (patch) | |
| tree | a1ca4e7334d3f67e34050656df028ef32be4c164 /lld | |
| parent | 55f1fbf005fef1e4024b2b44db0842f23fc5ea64 (diff) | |
| download | llvm-2b38f589301d7defef6099b57ecf45139010a5a7.zip llvm-2b38f589301d7defef6099b57ecf45139010a5a7.tar.gz llvm-2b38f589301d7defef6099b57ecf45139010a5a7.tar.bz2 | |
[llvm-objdump,ARM] Add PrettyPrinters for Arm and AArch64.
Most Arm disassemblers, including GNU objdump and Arm's own `fromelf`,
emit an instruction's raw encoding as a 32-bit words or (for Thumb)
one or two 16-bit halfwords, in logical order rather than according to
their storage endianness. This is generally easier to read: it matches
the encoding diagrams in the architecture spec, it matches the value
you'd write in a `.inst` directive, and it means that fields within
the instruction encoding that span more than one byte (such as branch
offsets or `SVC` immediates) can be read directly in the encoding
without having to mentally reverse the bytes.
llvm-objdump already has a system of PrettyPrinter subclasses which
makes it easy for a target to drop in its own preferred formatting.
This patch adds pretty-printers for all the Arm targets, so that
llvm-objdump will display Arm instruction encodings in their preferred
layout instead of little-endian and bytewise.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D130358
Diffstat (limited to 'lld')
51 files changed, 968 insertions, 968 deletions
diff --git a/lld/test/COFF/arm-thumb-thunks-multipass.s b/lld/test/COFF/arm-thumb-thunks-multipass.s index 267b225..18da135 100644 --- a/lld/test/COFF/arm-thumb-thunks-multipass.s +++ b/lld/test/COFF/arm-thumb-thunks-multipass.s @@ -51,20 +51,20 @@ far_func\i: .endr bx lr -// FUNC01: 403000: 41 f0 fc 87 bne.w 0x404ffc <.text+0x3ffc> -// FUNC01: 403004: 41 f0 ff 87 bne.w 0x405006 <.text+0x4006> +// FUNC01: 403000: f041 87fc bne.w 0x404ffc <.text+0x3ffc> +// FUNC01: 403004: f041 87ff bne.w 0x405006 <.text+0x4006> // Check that we only have two thunks here, even if we created the first // thunk twice (once in the first pass, then thrown away and recreated // in the second pass). -// FUNC01-THUNKS: 404ffa: 00 00 movs r0, r0 +// FUNC01-THUNKS: 404ffa: 0000 movs r0, r0 // The instruction above is padding from the .space -// FUNC01-THUNKS: 404ffc: 47 f2 1e 0c movw r12, #28702 -// FUNC01-THUNKS: 405000: c0 f2 20 0c movt r12, #32 -// FUNC01-THUNKS: 405004: e7 44 add pc, r12 -// FUNC01-THUNKS: 405006: 46 f6 f0 7c movw r12, #28656 -// FUNC01-THUNKS: 40500a: c0 f2 10 0c movt r12, #16 -// FUNC01-THUNKS: 40500e: e7 44 add pc, r12 +// FUNC01-THUNKS: 404ffc: f247 0c1e movw r12, #28702 +// FUNC01-THUNKS: 405000: f2c0 0c20 movt r12, #32 +// FUNC01-THUNKS: 405004: 44e7 add pc, r12 +// FUNC01-THUNKS: 405006: f646 7cf0 movw r12, #28656 +// FUNC01-THUNKS: 40500a: f2c0 0c10 movt r12, #16 +// FUNC01-THUNKS: 40500e: 44e7 add pc, r12 // The instruction below is padding from the .balign -// FUNC01-THUNKS: 405010: cc cc ldm r4!, {r2, r3, r6, r7} +// FUNC01-THUNKS: 405010: cccc ldm r4!, {r2, r3, r6, r7} diff --git a/lld/test/COFF/arm-thumb-thunks.s b/lld/test/COFF/arm-thumb-thunks.s index 868f368..2a176b0 100644 --- a/lld/test/COFF/arm-thumb-thunks.s +++ b/lld/test/COFF/arm-thumb-thunks.s @@ -48,28 +48,28 @@ func2: "??_C@string2": .asciz "bar" -// MAIN: 401000: 40 f0 05 80 bne.w 0x40100e <.text+0xe> -// MAIN: 401004: 40 f0 08 80 bne.w 0x401018 <.text+0x18> -// MAIN: 401008: 40 f0 01 80 bne.w 0x40100e <.text+0xe> -// MAIN: 40100c: 70 47 bx lr +// MAIN: 401000: f040 8005 bne.w 0x40100e <.text+0xe> +// MAIN: 401004: f040 8008 bne.w 0x401018 <.text+0x18> +// MAIN: 401008: f040 8001 bne.w 0x40100e <.text+0xe> +// MAIN: 40100c: 4770 bx lr // func1 thunk -// MAIN: 40100e: 40 f2 08 0c movw r12, #8 -// MAIN: 401012: c0 f2 10 0c movt r12, #16 -// MAIN: 401016: e7 44 add pc, r12 +// MAIN: 40100e: f240 0c08 movw r12, #8 +// MAIN: 401012: f2c0 0c10 movt r12, #16 +// MAIN: 401016: 44e7 add pc, r12 // func2 thunk -// MAIN: 401018: 40 f2 0e 0c movw r12, #14 -// MAIN: 40101c: c0 f2 20 0c movt r12, #32 -// MAIN: 401020: e7 44 add pc, r12 +// MAIN: 401018: f240 0c0e movw r12, #14 +// MAIN: 40101c: f2c0 0c20 movt r12, #32 +// MAIN: 401020: 44e7 add pc, r12 -// FUNC1: 501022: 40 f0 01 80 bne.w 0x501028 <.text+0x100028> -// FUNC1: 501026: 70 47 bx lr +// FUNC1: 501022: f040 8001 bne.w 0x501028 <.text+0x100028> +// FUNC1: 501026: 4770 bx lr // func2 thunk -// FUNC1: 501028: 4f f6 fe 7c movw r12, #65534 -// FUNC1: 50102c: c0 f2 0f 0c movt r12, #15 -// FUNC1: 501030: e7 44 add pc, r12 +// FUNC1: 501028: f64f 7cfe movw r12, #65534 +// FUNC1: 50102c: f2c0 0c0f movt r12, #15 +// FUNC1: 501030: 44e7 add pc, r12 -// FUNC2: 601032: 42 f2 00 00 movw r0, #8192 -// FUNC2: 601036: c0 f2 60 00 movt r0, #96 -// FUNC2: 60103a: 42 f2 03 01 movw r1, #8195 -// FUNC2: 60103e: c0 f2 60 01 movt r1, #96 -// FUNC2: 601042: 70 47 bx lr +// FUNC2: 601032: f242 0000 movw r0, #8192 +// FUNC2: 601036: f2c0 0060 movt r0, #96 +// FUNC2: 60103a: f242 0103 movw r1, #8195 +// FUNC2: 60103e: f2c0 0160 movt r1, #96 +// FUNC2: 601042: 4770 bx lr diff --git a/lld/test/COFF/arm64-delayimport.yaml b/lld/test/COFF/arm64-delayimport.yaml index 583103f..b9e1c32 100644 --- a/lld/test/COFF/arm64-delayimport.yaml +++ b/lld/test/COFF/arm64-delayimport.yaml @@ -5,34 +5,34 @@ # RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix DISASM # RUN: llvm-readobj --coff-imports %t.exe | FileCheck %s -check-prefix IMPORTS -# DISASM: 140001014: 11 00 00 d0 adrp x17, 0x140003000 -# DISASM: 140001018: 31 22 00 91 add x17, x17, #8 -# DISASM: 14000101c: 01 00 00 14 b 0x140001020 <.text+0x20> -# DISASM: 140001020: fd 7b b3 a9 stp x29, x30, [sp, #-208]! -# DISASM: 140001024: fd 03 00 91 mov x29, sp -# DISASM: 140001028: e0 07 01 a9 stp x0, x1, [sp, #16] -# DISASM: 14000102c: e2 0f 02 a9 stp x2, x3, [sp, #32] -# DISASM: 140001030: e4 17 03 a9 stp x4, x5, [sp, #48] -# DISASM: 140001034: e6 1f 04 a9 stp x6, x7, [sp, #64] -# DISASM: 140001038: e0 87 02 ad stp q0, q1, [sp, #80] -# DISASM: 14000103c: e2 8f 03 ad stp q2, q3, [sp, #112] -# DISASM: 140001040: e4 97 04 ad stp q4, q5, [sp, #144] -# DISASM: 140001044: e6 9f 05 ad stp q6, q7, [sp, #176] -# DISASM: 140001048: e1 03 11 aa mov x1, x17 -# DISASM: 14000104c: 00 00 00 b0 adrp x0, 0x140002000 -# DISASM: 140001050: 00 00 00 91 add x0, x0, #0 -# DISASM: 140001054: eb ff ff 97 bl 0x140001000 <.text> -# DISASM: 140001058: f0 03 00 aa mov x16, x0 -# DISASM: 14000105c: e6 9f 45 ad ldp q6, q7, [sp, #176] -# DISASM: 140001060: e4 97 44 ad ldp q4, q5, [sp, #144] -# DISASM: 140001064: e2 8f 43 ad ldp q2, q3, [sp, #112] -# DISASM: 140001068: e0 87 42 ad ldp q0, q1, [sp, #80] -# DISASM: 14000106c: e6 1f 44 a9 ldp x6, x7, [sp, #64] -# DISASM: 140001070: e4 17 43 a9 ldp x4, x5, [sp, #48] -# DISASM: 140001074: e2 0f 42 a9 ldp x2, x3, [sp, #32] -# DISASM: 140001078: e0 07 41 a9 ldp x0, x1, [sp, #16] -# DISASM: 14000107c: fd 7b cd a8 ldp x29, x30, [sp], #208 -# DISASM: 140001080: 00 02 1f d6 br x16 +# DISASM: 140001014: d0000011 adrp x17, 0x140003000 +# DISASM: 140001018: 91002231 add x17, x17, #8 +# DISASM: 14000101c: 14000001 b 0x140001020 <.text+0x20> +# DISASM: 140001020: a9b37bfd stp x29, x30, [sp, #-208]! +# DISASM: 140001024: 910003fd mov x29, sp +# DISASM: 140001028: a90107e0 stp x0, x1, [sp, #16] +# DISASM: 14000102c: a9020fe2 stp x2, x3, [sp, #32] +# DISASM: 140001030: a90317e4 stp x4, x5, [sp, #48] +# DISASM: 140001034: a9041fe6 stp x6, x7, [sp, #64] +# DISASM: 140001038: ad0287e0 stp q0, q1, [sp, #80] +# DISASM: 14000103c: ad038fe2 stp q2, q3, [sp, #112] +# DISASM: 140001040: ad0497e4 stp q4, q5, [sp, #144] +# DISASM: 140001044: ad059fe6 stp q6, q7, [sp, #176] +# DISASM: 140001048: aa1103e1 mov x1, x17 +# DISASM: 14000104c: b0000000 adrp x0, 0x140002000 +# DISASM: 140001050: 91000000 add x0, x0, #0 +# DISASM: 140001054: 97ffffeb bl 0x140001000 <.text> +# DISASM: 140001058: aa0003f0 mov x16, x0 +# DISASM: 14000105c: ad459fe6 ldp q6, q7, [sp, #176] +# DISASM: 140001060: ad4497e4 ldp q4, q5, [sp, #144] +# DISASM: 140001064: ad438fe2 ldp q2, q3, [sp, #112] +# DISASM: 140001068: ad4287e0 ldp q0, q1, [sp, #80] +# DISASM: 14000106c: a9441fe6 ldp x6, x7, [sp, #64] +# DISASM: 140001070: a94317e4 ldp x4, x5, [sp, #48] +# DISASM: 140001074: a9420fe2 ldp x2, x3, [sp, #32] +# DISASM: 140001078: a94107e0 ldp x0, x1, [sp, #16] +# DISASM: 14000107c: a8cd7bfd ldp x29, x30, [sp], #208 +# DISASM: 140001080: d61f0200 br x16 # IMPORTS: Format: COFF-ARM64 # IMPORTS: Arch: aarch64 diff --git a/lld/test/COFF/arm64-import2.test b/lld/test/COFF/arm64-import2.test index 1122ab8..1654067 100644 --- a/lld/test/COFF/arm64-import2.test +++ b/lld/test/COFF/arm64-import2.test @@ -8,23 +8,23 @@ # BEFORE: Disassembly of section .text: # BEFORE-EMPTY: -# BEFORE: 0: 00 00 00 94 bl 0x0 -# BEFORE: 4: 00 00 00 94 bl 0x4 -# BEFORE: 8: c0 03 5f d6 ret +# BEFORE: 0: 94000000 bl 0x0 +# BEFORE: 4: 94000000 bl 0x4 +# BEFORE: 8: d65f03c0 ret # BEFORE: c: ff <unknown> # AFTER: Disassembly of section .text: # AFTER-EMPTY: -# AFTER: 140001000: 04 00 00 94 bl 0x140001010 -# AFTER: 140001004: 06 00 00 94 bl 0x14000101c -# AFTER: 140001008: c0 03 5f d6 ret -# AFTER: 14000100c: ff cc cc cc <unknown> -# AFTER: 140001010: 10 00 00 b0 adrp x16, 0x140002000 -# AFTER: 140001014: 10 32 40 f9 ldr x16, [x16, #96] -# AFTER: 140001018: 00 02 1f d6 br x16 -# AFTER: 14000101c: 10 00 00 b0 adrp x16, 0x140002000 -# AFTER: 140001020: 10 3a 40 f9 ldr x16, [x16, #112] -# AFTER: 140001024: 00 02 1f d6 br x16 +# AFTER: 140001000: 94000004 bl 0x140001010 +# AFTER: 140001004: 94000006 bl 0x14000101c +# AFTER: 140001008: d65f03c0 ret +# AFTER: 14000100c: ccccccff <unknown> +# AFTER: 140001010: b0000010 adrp x16, 0x140002000 +# AFTER: 140001014: f9403210 ldr x16, [x16, #96] +# AFTER: 140001018: d61f0200 br x16 +# AFTER: 14000101c: b0000010 adrp x16, 0x140002000 +# AFTER: 140001020: f9403a10 ldr x16, [x16, #112] +# AFTER: 140001024: d61f0200 br x16 # IMPORTS: Import { # IMPORTS: Name: library.dll diff --git a/lld/test/COFF/arm64-relocs-imports.test b/lld/test/COFF/arm64-relocs-imports.test index c2695dd..7874aed 100644 --- a/lld/test/COFF/arm64-relocs-imports.test +++ b/lld/test/COFF/arm64-relocs-imports.test @@ -7,94 +7,94 @@ # BEFORE: Disassembly of section .text: # BEFORE-EMPTY: -# BEFORE: 0: fe 0f 1f f8 str x30, [sp, #-16]! -# BEFORE: 4: 00 00 00 90 adrp x0, 0x0 -# BEFORE: 8: 00 08 00 91 add x0, x0, #2 -# BEFORE: c: 00 00 00 94 bl 0xc -# BEFORE: 10: 00 01 40 39 ldrb w0, [x8] -# BEFORE: 14: 00 01 40 79 ldrh w0, [x8] -# BEFORE: 18: 00 01 40 b9 ldr w0, [x8] -# BEFORE: 1c: 00 01 40 f9 ldr x0, [x8] -# BEFORE: 20: 00 01 00 39 strb w0, [x8] -# BEFORE: 24: 00 01 00 79 strh w0, [x8] -# BEFORE: 28: 00 01 00 b9 str w0, [x8] -# BEFORE: 2c: 00 01 00 f9 str x0, [x8] -# BEFORE: 30: 00 01 40 3d ldr b0, [x8] -# BEFORE: 34: 00 01 40 7d ldr h0, [x8] -# BEFORE: 38: 00 01 40 bd ldr s0, [x8] -# BEFORE: 3c: 00 01 40 fd ldr d0, [x8] -# BEFORE: 40: 00 01 c0 3d ldr q0, [x8] -# BEFORE: 44: 00 01 00 3d str b0, [x8] -# BEFORE: 48: 00 01 00 7d str h0, [x8] -# BEFORE: 4c: 00 01 00 bd str s0, [x8] -# BEFORE: 50: 00 01 00 fd str d0, [x8] -# BEFORE: 54: 00 01 80 3d str q0, [x8] -# BEFORE: 58: 00 05 40 f9 ldr x0, [x8, #8] -# BEFORE: 5c: 20 1a 01 b0 adrp x0, 0x2345000 -# BEFORE: 60: 00 fc 4f f9 ldr x0, [x0, #8184] -# BEFORE: 64: e0 03 1f 2a mov w0, wzr -# BEFORE: 68: fe 07 41 f8 ldr x30, [sp], #16 -# BEFORE: 6c: c0 03 5f d6 ret -# BEFORE: 70: 08 00 00 00 udf #8 -# BEFORE: 74: 00 00 00 00 udf #0 -# BEFORE: 78: 01 00 00 00 udf #1 -# BEFORE: 7c: 01 00 00 00 udf #1 -# BEFORE: 80: 00 00 00 91 add x0, x0, #0 -# BEFORE: 84: 00 00 40 91 add x0, x0, #0, lsl #12 -# BEFORE: 88: 00 00 40 f9 ldr x0, [x0] -# BEFORE: 8c: 01 00 00 00 udf #1 -# BEFORE: 90: 20 1a 09 30 adr x0, #74565 -# BEFORE: 94: 01 00 00 54 b.ne 0x94 -# BEFORE: 98: 00 00 00 36 tbz w0, #0, 0x98 -# BEFORE: 9c: 01 00 00 00 udf #1 -# BEFORE: a0: 02 00 80 90 adrp x2, 0xffffffff00000000 +# BEFORE: 0: f81f0ffe str x30, [sp, #-16]! +# BEFORE: 4: 90000000 adrp x0, 0x0 +# BEFORE: 8: 91000800 add x0, x0, #2 +# BEFORE: c: 94000000 bl 0xc +# BEFORE: 10: 39400100 ldrb w0, [x8] +# BEFORE: 14: 79400100 ldrh w0, [x8] +# BEFORE: 18: b9400100 ldr w0, [x8] +# BEFORE: 1c: f9400100 ldr x0, [x8] +# BEFORE: 20: 39000100 strb w0, [x8] +# BEFORE: 24: 79000100 strh w0, [x8] +# BEFORE: 28: b9000100 str w0, [x8] +# BEFORE: 2c: f9000100 str x0, [x8] +# BEFORE: 30: 3d400100 ldr b0, [x8] +# BEFORE: 34: 7d400100 ldr h0, [x8] +# BEFORE: 38: bd400100 ldr s0, [x8] +# BEFORE: 3c: fd400100 ldr d0, [x8] +# BEFORE: 40: 3dc00100 ldr q0, [x8] +# BEFORE: 44: 3d000100 str b0, [x8] +# BEFORE: 48: 7d000100 str h0, [x8] +# BEFORE: 4c: bd000100 str s0, [x8] +# BEFORE: 50: fd000100 str d0, [x8] +# BEFORE: 54: 3d800100 str q0, [x8] +# BEFORE: 58: f9400500 ldr x0, [x8, #8] +# BEFORE: 5c: b0011a20 adrp x0, 0x2345000 +# BEFORE: 60: f94ffc00 ldr x0, [x0, #8184] +# BEFORE: 64: 2a1f03e0 mov w0, wzr +# BEFORE: 68: f84107fe ldr x30, [sp], #16 +# BEFORE: 6c: d65f03c0 ret +# BEFORE: 70: 00000008 udf #8 +# BEFORE: 74: 00000000 udf #0 +# BEFORE: 78: 00000001 udf #1 +# BEFORE: 7c: 00000001 udf #1 +# BEFORE: 80: 91000000 add x0, x0, #0 +# BEFORE: 84: 91400000 add x0, x0, #0, lsl #12 +# BEFORE: 88: f9400000 ldr x0, [x0] +# BEFORE: 8c: 00000001 udf #1 +# BEFORE: 90: 30091a20 adr x0, #74565 +# BEFORE: 94: 54000001 b.ne 0x94 +# BEFORE: 98: 36000000 tbz w0, #0, 0x98 +# BEFORE: 9c: 00000001 udf #1 +# BEFORE: a0: 90800002 adrp x2, 0xffffffff00000000 # AFTER: Disassembly of section .text: # AFTER-EMPTY: -# AFTER: 140001000: fe 0f 1f f8 str x30, [sp, #-16]! -# AFTER: 140001004: 00 00 00 b0 adrp x0, 0x140002000 -# AFTER: 140001008: 00 18 00 91 add x0, x0, #6 -# AFTER: 14000100c: 26 00 00 94 bl 0x1400010a4 -# AFTER: 140001010: 00 21 40 39 ldrb w0, [x8, #8] -# AFTER: 140001014: 00 11 40 79 ldrh w0, [x8, #8] -# AFTER: 140001018: 00 09 40 b9 ldr w0, [x8, #8] -# AFTER: 14000101c: 00 05 40 f9 ldr x0, [x8, #8] -# AFTER: 140001020: 00 21 00 39 strb w0, [x8, #8] -# AFTER: 140001024: 00 11 00 79 strh w0, [x8, #8] -# AFTER: 140001028: 00 09 00 b9 str w0, [x8, #8] -# AFTER: 14000102c: 00 05 00 f9 str x0, [x8, #8] -# AFTER: 140001030: 00 41 40 3d ldr b0, [x8, #16] -# AFTER: 140001034: 00 21 40 7d ldr h0, [x8, #16] -# AFTER: 140001038: 00 11 40 bd ldr s0, [x8, #16] -# AFTER: 14000103c: 00 09 40 fd ldr d0, [x8, #16] -# AFTER: 140001040: 00 05 c0 3d ldr q0, [x8, #16] -# AFTER: 140001044: 00 41 00 3d str b0, [x8, #16] -# AFTER: 140001048: 00 21 00 7d str h0, [x8, #16] -# AFTER: 14000104c: 00 11 00 bd str s0, [x8, #16] -# AFTER: 140001050: 00 09 00 fd str d0, [x8, #16] -# AFTER: 140001054: 00 05 80 3d str q0, [x8, #16] -# AFTER: 140001058: 00 09 40 f9 ldr x0, [x8, #16] -# AFTER: 14000105c: 00 00 00 f0 adrp x0, 0x140004000 -# AFTER: 140001060: 00 fc 47 f9 ldr x0, [x0, #4088] -# AFTER: 140001064: e0 03 1f 2a mov w0, wzr -# AFTER: 140001068: fe 07 41 f8 ldr x30, [sp], #16 -# AFTER: 14000106c: c0 03 5f d6 ret -# AFTER: 140001070: 10 20 00 40 <unknown> -# AFTER: 140001074: 01 00 00 00 udf #1 -# AFTER: 140001078: 09 20 00 00 udf #8201 -# AFTER: 14000107c: 09 00 00 00 udf #9 -# AFTER: 140001080: 00 20 0e 91 add x0, x0, #904 -# AFTER: 140001084: 00 04 40 91 add x0, x0, #1, lsl #12 -# AFTER: 140001088: 00 c4 41 f9 ldr x0, [x0, #904] -# AFTER: 14000108c: 03 00 00 00 udf #3 -# AFTER: 140001090: e0 95 09 30 adr x0, #78525 -# AFTER: 140001094: 81 00 00 54 b.ne 0x1400010a4 -# AFTER: 140001098: 60 00 00 36 tbz w0, #0, 0x1400010a4 -# AFTER: 14000109c: 61 ff ff ff <unknown> -# AFTER: 1400010a0: 02 f8 ff b0 adrp x2, 0x13ff02000 -# AFTER: 1400010a4: 10 00 00 b0 adrp x16, 0x140002000 -# AFTER: 1400010a8: 10 2a 40 f9 ldr x16, [x16, #80] -# AFTER: 1400010ac: 00 02 1f d6 br x16 +# AFTER: 140001000: f81f0ffe str x30, [sp, #-16]! +# AFTER: 140001004: b0000000 adrp x0, 0x140002000 +# AFTER: 140001008: 91001800 add x0, x0, #6 +# AFTER: 14000100c: 94000026 bl 0x1400010a4 +# AFTER: 140001010: 39402100 ldrb w0, [x8, #8] +# AFTER: 140001014: 79401100 ldrh w0, [x8, #8] +# AFTER: 140001018: b9400900 ldr w0, [x8, #8] +# AFTER: 14000101c: f9400500 ldr x0, [x8, #8] +# AFTER: 140001020: 39002100 strb w0, [x8, #8] +# AFTER: 140001024: 79001100 strh w0, [x8, #8] +# AFTER: 140001028: b9000900 str w0, [x8, #8] +# AFTER: 14000102c: f9000500 str x0, [x8, #8] +# AFTER: 140001030: 3d404100 ldr b0, [x8, #16] +# AFTER: 140001034: 7d402100 ldr h0, [x8, #16] +# AFTER: 140001038: bd401100 ldr s0, [x8, #16] +# AFTER: 14000103c: fd400900 ldr d0, [x8, #16] +# AFTER: 140001040: 3dc00500 ldr q0, [x8, #16] +# AFTER: 140001044: 3d004100 str b0, [x8, #16] +# AFTER: 140001048: 7d002100 str h0, [x8, #16] +# AFTER: 14000104c: bd001100 str s0, [x8, #16] +# AFTER: 140001050: fd000900 str d0, [x8, #16] +# AFTER: 140001054: 3d800500 str q0, [x8, #16] +# AFTER: 140001058: f9400900 ldr x0, [x8, #16] +# AFTER: 14000105c: f0000000 adrp x0, 0x140004000 +# AFTER: 140001060: f947fc00 ldr x0, [x0, #4088] +# AFTER: 140001064: 2a1f03e0 mov w0, wzr +# AFTER: 140001068: f84107fe ldr x30, [sp], #16 +# AFTER: 14000106c: d65f03c0 ret +# AFTER: 140001070: 40002010 <unknown> +# AFTER: 140001074: 00000001 udf #1 +# AFTER: 140001078: 00002009 udf #8201 +# AFTER: 14000107c: 00000009 udf #9 +# AFTER: 140001080: 910e2000 add x0, x0, #904 +# AFTER: 140001084: 91400400 add x0, x0, #1, lsl #12 +# AFTER: 140001088: f941c400 ldr x0, [x0, #904] +# AFTER: 14000108c: 00000003 udf #3 +# AFTER: 140001090: 300995e0 adr x0, #78525 +# AFTER: 140001094: 54000081 b.ne 0x1400010a4 +# AFTER: 140001098: 36000060 tbz w0, #0, 0x1400010a4 +# AFTER: 14000109c: ffffff61 <unknown> +# AFTER: 1400010a0: b0fff802 adrp x2, 0x13ff02000 +# AFTER: 1400010a4: b0000010 adrp x16, 0x140002000 +# AFTER: 1400010a8: f9402a10 ldr x16, [x16, #80] +# AFTER: 1400010ac: d61f0200 br x16 --- !COFF header: diff --git a/lld/test/COFF/arm64-thunks.s b/lld/test/COFF/arm64-thunks.s index 4428bf79..86760ed 100644 --- a/lld/test/COFF/arm64-thunks.s +++ b/lld/test/COFF/arm64-thunks.s @@ -27,17 +27,17 @@ func2: ret // DISASM: 0000000140001000 <.text>: -// DISASM: 140001000: 40 00 00 36 tbz w0, #0, 0x140001008 <.text+0x8> -// DISASM: 140001004: c0 03 5f d6 ret -// DISASM: 140001008: 50 00 00 90 adrp x16, 0x140009000 -// DISASM: 14000100c: 10 52 00 91 add x16, x16, #20 -// DISASM: 140001010: 00 02 1f d6 br x16 +// DISASM: 140001000: 36000040 tbz w0, #0, 0x140001008 <.text+0x8> +// DISASM: 140001004: d65f03c0 ret +// DISASM: 140001008: 90000050 adrp x16, 0x140009000 +// DISASM: 14000100c: 91005210 add x16, x16, #20 +// DISASM: 140001010: d61f0200 br x16 -// DISASM: 140009014: 60 00 00 36 tbz w0, #0, 0x140009020 <.text+0x8020> -// DISASM: 140009018: c0 03 5f d6 ret +// DISASM: 140009014: 36000060 tbz w0, #0, 0x140009020 <.text+0x8020> +// DISASM: 140009018: d65f03c0 ret -// DISASM: 140009020: 50 00 00 90 adrp x16, 0x140011000 -// DISASM: 140009024: 10 b2 00 91 add x16, x16, #44 -// DISASM: 140009028: 00 02 1f d6 br x16 +// DISASM: 140009020: 90000050 adrp x16, 0x140011000 +// DISASM: 140009024: 9100b210 add x16, x16, #44 +// DISASM: 140009028: d61f0200 br x16 -// DISASM: 14001102c: c0 03 5f d6 ret +// DISASM: 14001102c: d65f03c0 ret diff --git a/lld/test/COFF/armnt-blx23t.test b/lld/test/COFF/armnt-blx23t.test index 66a5222..6cdddad 100644 --- a/lld/test/COFF/armnt-blx23t.test +++ b/lld/test/COFF/armnt-blx23t.test @@ -7,25 +7,25 @@ # BEFORE: Disassembly of section .text: # BEFORE-EMPTY: -# BEFORE: 0: 70 47 bx lr -# BEFORE: 2: 00 bf nop -# BEFORE: 4: 2d e9 00 48 push.w {r11, lr} -# BEFORE: 8: eb 46 mov r11, sp -# BEFORE: a: 20 20 movs r0, #32 -# BEFORE: c: 00 f0 00 f8 bl {{.+}} @ imm = #0 -# BEFORE: 10: 01 30 adds r0, #1 -# BEFORE: 12: bd e8 00 88 pop.w {r11, pc} +# BEFORE: 0: 4770 bx lr +# BEFORE: 2: bf00 nop +# BEFORE: 4: e92d 4800 push.w {r11, lr} +# BEFORE: 8: 46eb mov r11, sp +# BEFORE: a: 2020 movs r0, #32 +# BEFORE: c: f000 f800 bl {{.+}} @ imm = #0 +# BEFORE: 10: 3001 adds r0, #1 +# BEFORE: 12: e8bd 8800 pop.w {r11, pc} # AFTER: Disassembly of section .text: # AFTER-EMPTY: -# AFTER: 401000: 70 47 bx lr -# AFTER: 401002: 00 bf nop -# AFTER: 401004: 2d e9 00 48 push.w {r11, lr} -# AFTER: 401008: eb 46 mov r11, sp -# AFTER: 40100a: 20 20 movs r0, #32 -# AFTER: 40100c: ff f7 f8 ff bl 0x401000 <.text> -# AFTER: 401010: 01 30 adds r0, #1 -# AFTER: 401012: bd e8 00 88 pop.w {r11, pc} +# AFTER: 401000: 4770 bx lr +# AFTER: 401002: bf00 nop +# AFTER: 401004: e92d 4800 push.w {r11, lr} +# AFTER: 401008: 46eb mov r11, sp +# AFTER: 40100a: 2020 movs r0, #32 +# AFTER: 40100c: f7ff fff8 bl 0x401000 <.text> +# AFTER: 401010: 3001 adds r0, #1 +# AFTER: 401012: e8bd 8800 pop.w {r11, pc} --- !COFF header: diff --git a/lld/test/COFF/armnt-branch24t.test b/lld/test/COFF/armnt-branch24t.test index 9a8f463..cf94c63 100644 --- a/lld/test/COFF/armnt-branch24t.test +++ b/lld/test/COFF/armnt-branch24t.test @@ -7,18 +7,18 @@ # BEFORE: Disassembly of section .text: # BEFORE-EMPTY: -# BEFORE: 0: 70 47 bx lr -# BEFORE: 2: 00 bf nop -# BEFORE: 4: 20 20 movs r0, #32 -# BEFORE: 6: 00 f0 00 b8 b.w {{.+}} @ imm = #0 +# BEFORE: 0: 4770 bx lr +# BEFORE: 2: bf00 nop +# BEFORE: 4: 2020 movs r0, #32 +# BEFORE: 6: f000 b800 b.w {{.+}} @ imm = #0 # AFTER: Disassembly of section .text: # AFTER-EMPTY: # AFTER: <.text>: -# AFTER: 401000: 70 47 bx lr -# AFTER: 401002: 00 bf nop -# AFTER: 401004: 20 20 movs r0, #32 -# AFTER: 401006: ff f7 fb bf b.w 0x401000 <.text> +# AFTER: 401000: 4770 bx lr +# AFTER: 401002: bf00 nop +# AFTER: 401004: 2020 movs r0, #32 +# AFTER: 401006: f7ff bffb b.w 0x401000 <.text> --- !COFF header: diff --git a/lld/test/COFF/armnt-mov32t-exec.test b/lld/test/COFF/armnt-mov32t-exec.test index 42528af..23a3e33 100644 --- a/lld/test/COFF/armnt-mov32t-exec.test +++ b/lld/test/COFF/armnt-mov32t-exec.test @@ -7,19 +7,19 @@ # BEFORE: Disassembly of section .text: # BEFORE-EMPTY: -# BEFORE: 0: 70 47 bx lr -# BEFORE: 2: 00 bf nop -# BEFORE: 4: 40 f2 00 00 movw r0, #0 -# BEFORE: 8: c0 f2 00 00 movt r0, #0 -# BEFORE: c: 70 47 bx lr +# BEFORE: 0: 4770 bx lr +# BEFORE: 2: bf00 nop +# BEFORE: 4: f240 0000 movw r0, #0 +# BEFORE: 8: f2c0 0000 movt r0, #0 +# BEFORE: c: 4770 bx lr # AFTER: Disassembly of section .text: # AFTER-EMPTY: -# AFTER: 1000: 70 47 bx lr -# AFTER: 1002: 00 bf nop -# AFTER: 1004: 41 f2 01 00 movw r0, #4097 -# AFTER: 1008: c0 f2 40 00 movt r0, #64 -# AFTER: 100c: 70 47 bx lr +# AFTER: 1000: 4770 bx lr +# AFTER: 1002: bf00 nop +# AFTER: 1004: f241 0001 movw r0, #4097 +# AFTER: 1008: f2c0 0040 movt r0, #64 +# AFTER: 100c: 4770 bx lr --- !COFF header: diff --git a/lld/test/COFF/armnt-movt32t.test b/lld/test/COFF/armnt-movt32t.test index f87dbd1..61d3c1e 100644 --- a/lld/test/COFF/armnt-movt32t.test +++ b/lld/test/COFF/armnt-movt32t.test @@ -7,15 +7,15 @@ # BEFORE: Disassembly of section .text: # BEFORE-EMPTY: -# BEFORE: 0: 40 f2 00 00 movw r0, #0 -# BEFORE: 4: c0 f2 00 00 movt r0, #0 -# BEFORE: 8: 70 47 bx lr +# BEFORE: 0: f240 0000 movw r0, #0 +# BEFORE: 4: f2c0 0000 movt r0, #0 +# BEFORE: 8: 4770 bx lr # AFTER: Disassembly of section .text: # AFTER-EMPTY: -# AFTER: 0: 42 f2 00 00 movw r0, #8192 -# AFTER: 4: c0 f2 40 00 movt r0, #64 -# AFTER: 8: 70 47 bx lr +# AFTER: 0: f242 0000 movw r0, #8192 +# AFTER: 4: f2c0 0040 movt r0, #64 +# AFTER: 8: 4770 bx lr --- !COFF header: diff --git a/lld/test/COFF/delayimports-armnt.yaml b/lld/test/COFF/delayimports-armnt.yaml index 42ed405..26fb7e3 100644 --- a/lld/test/COFF/delayimports-armnt.yaml +++ b/lld/test/COFF/delayimports-armnt.yaml @@ -52,20 +52,20 @@ # BASEREL-NEXT: ] # # DISASM: 00401000 <.text>: -# DISASM: 40100c: 43 f2 08 0c movw r12, #12296 -# DISASM-NEXT: c0 f2 40 0c movt r12, #64 -# DISASM-NEXT: 00 f0 00 b8 b.w {{.+}} @ imm = #0 -# DISASM-NEXT: 2d e9 0f 48 push.w {r0, r1, r2, r3, r11, lr} -# DISASM-NEXT: 0d f2 10 0b addw r11, sp, #16 -# DISASM-NEXT: 2d ed 10 0b vpush {d0, d1, d2, d3, d4, d5, d6, d7} -# DISASM-NEXT: 61 46 mov r1, r12 -# DISASM-NEXT: 42 f2 00 00 movw r0, #8192 -# DISASM-NEXT: c0 f2 40 00 movt r0, #64 -# DISASM-NEXT: ff f7 e7 ff bl 0x401000 <.text> -# DISASM-NEXT: 84 46 mov r12, r0 -# DISASM-NEXT: bd ec 10 0b vpop {d0, d1, d2, d3, d4, d5, d6, d7} -# DISASM-NEXT: bd e8 0f 48 pop.w {r0, r1, r2, r3, r11, lr} -# DISASM-NEXT: 60 47 bx r12 +# DISASM: 40100c: f243 0c08 movw r12, #12296 +# DISASM-NEXT: f2c0 0c40 movt r12, #64 +# DISASM-NEXT: f000 b800 b.w {{.+}} @ imm = #0 +# DISASM-NEXT: e92d 480f push.w {r0, r1, r2, r3, r11, lr} +# DISASM-NEXT: f20d 0b10 addw r11, sp, #16 +# DISASM-NEXT: ed2d 0b10 vpush {d0, d1, d2, d3, d4, d5, d6, d7} +# DISASM-NEXT: 4661 mov r1, r12 +# DISASM-NEXT: f242 0000 movw r0, #8192 +# DISASM-NEXT: f2c0 0040 movt r0, #64 +# DISASM-NEXT: f7ff ffe7 bl 0x401000 <.text> +# DISASM-NEXT: 4684 mov r12, r0 +# DISASM-NEXT: ecbd 0b10 vpop {d0, d1, d2, d3, d4, d5, d6, d7} +# DISASM-NEXT: e8bd 480f pop.w {r0, r1, r2, r3, r11, lr} +# DISASM-NEXT: 4760 bx r12 --- !COFF header: diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-address.s b/lld/test/ELF/aarch64-cortex-a53-843419-address.s index fcf5f40..59ab91d 100644 --- a/lld/test/ELF/aarch64-cortex-a53-843419-address.s +++ b/lld/test/ELF/aarch64-cortex-a53-843419-address.s @@ -38,10 +38,10 @@ // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at FF8 in unpatched output. // CHECK: <t3_ff8_ldr>: -// CHECK-NEXT: ff8: 20 00 00 d0 adrp x0, 0x6000 -// CHECK-NEXT: ffc: 21 00 40 f9 ldr x1, [x1] -// CHECK-NEXT: 1000: f9 0f 00 14 b 0x4fe4 -// CHECK-NEXT: 1004: c0 03 5f d6 ret +// CHECK-NEXT: ff8: d0000020 adrp x0, 0x6000 +// CHECK-NEXT: ffc: f9400021 ldr x1, [x1] +// CHECK-NEXT: 1000: 14000ff9 b 0x4fe4 +// CHECK-NEXT: 1004: d65f03c0 ret .section .text.01, "ax", %progbits .balign 4096 .space 4096 - 8 @@ -60,10 +60,10 @@ t3_ff8_ldr: $x.999: // CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 1FFC in unpatched output. // CHECK: <t3_ffc_ldrsimd>: -// CHECK-NEXT: 1ffc: 20 00 00 b0 adrp x0, 0x6000 -// CHECK-NEXT: 2000: 21 00 40 bd ldr s1, [x1] -// CHECK-NEXT: 2004: fa 0b 00 14 b 0x4fec -// CHECK-NEXT: 2008: c0 03 5f d6 ret +// CHECK-NEXT: 1ffc: b0000020 adrp x0, 0x6000 +// CHECK-NEXT: 2000: bd400021 ldr s1, [x1] +// CHECK-NEXT: 2004: 14000bfa b 0x4fec +// CHECK-NEXT: 2008: d65f03c0 ret .globl t3_ffc_ldrsimd .type t3_ffc_ldrsimd, %function .space 4096 - 12 @@ -97,10 +97,10 @@ t3_ff8_ldralldata: // CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 3FF8 in unpatched output. // CHECK: <t3_ffc_ldr>: -// CHECK-NEXT: 3ff8: 00 00 00 f0 adrp x0, 0x6000 -// CHECK-NEXT: 3ffc: 21 00 40 f9 ldr x1, [x1] -// CHECK-NEXT: 4000: fd 03 00 14 b 0x4ff4 -// CHECK-NEXT: 4004: c0 03 5f d6 ret +// CHECK-NEXT: 3ff8: f0000000 adrp x0, 0x6000 +// CHECK-NEXT: 3ffc: f9400021 ldr x1, [x1] +// CHECK-NEXT: 4000: 140003fd b 0x4ff4 +// CHECK-NEXT: 4004: d65f03c0 ret .space 4096 - 12 .globl t3_ffc_ldr .type t3_ffc_ldr, %function @@ -111,14 +111,14 @@ t3_ff8_ldralldata: ret // CHECK: <__CortexA53843419_1000>: -// CHECK-NEXT: 4fe4: 00 0c 40 f9 ldr x0, [x0, #24] -// CHECK-NEXT: 4fe8: 07 f0 ff 17 b 0x1004 +// CHECK-NEXT: 4fe4: f9400c00 ldr x0, [x0, #24] +// CHECK-NEXT: 4fe8: 17fff007 b 0x1004 // CHECK: <__CortexA53843419_2004>: -// CHECK-NEXT: 4fec: 02 0c 40 f9 ldr x2, [x0, #24] -// CHECK-NEXT: 4ff0: 06 f4 ff 17 b 0x2008 +// CHECK-NEXT: 4fec: f9400c02 ldr x2, [x0, #24] +// CHECK-NEXT: 4ff0: 17fff406 b 0x2008 // CHECK: <__CortexA53843419_4000>: -// CHECK-NEXT: 4ff4: 00 0c 40 f9 ldr x0, [x0, #24] -// CHECK-NEXT: 4ff8: 03 fc ff 17 b 0x4004 +// CHECK-NEXT: 4ff4: f9400c00 ldr x0, [x0, #24] +// CHECK-NEXT: 4ff8: 17fffc03 b 0x4004 .section .text.02, "ax", %progbits .space 4096 - 36 @@ -129,10 +129,10 @@ t3_ff8_ldralldata: // CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 4FFC in unpatched output // CHECK: <t3_ffc_str>: -// CHECK-NEXT: 4ffc: 00 00 00 d0 adrp x0, 0x6000 -// CHECK-NEXT: 5000: 21 00 00 f9 str x1, [x1] -// CHECK-NEXT: 5004: fb 03 00 14 b 0x5ff0 -// CHECK-NEXT: 5008: c0 03 5f d6 ret +// CHECK-NEXT: 4ffc: d0000000 adrp x0, 0x6000 +// CHECK-NEXT: 5000: f9000021 str x1, [x1] +// CHECK-NEXT: 5004: 140003fb b 0x5ff0 +// CHECK-NEXT: 5008: d65f03c0 ret .section .newisd, "ax", %progbits .globl t3_ffc_str @@ -145,8 +145,8 @@ t3_ffc_str: .space 4096 - 28 // CHECK: <__CortexA53843419_5004>: -// CHECK-NEXT: 5ff0: 00 0c 40 f9 ldr x0, [x0, #24] -// CHECK-NEXT: 5ff4: 05 fc ff 17 b 0x5008 +// CHECK-NEXT: 5ff0: f9400c00 ldr x0, [x0, #24] +// CHECK-NEXT: 5ff4: 17fffc05 b 0x5008 // Start a new OutputSection (see Linker Script) so the // start address will be affected by any patches added to previous @@ -154,10 +154,10 @@ t3_ffc_str: //CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 5FF8 in unpatched output // CHECK: <t3_ff8_str>: -// CHECK-NEXT: 5ff8: 00 00 00 b0 adrp x0, 0x6000 -// CHECK-NEXT: 5ffc: 21 00 00 f9 str x1, [x1] -// CHECK-NEXT: 6000: 03 00 00 14 b 0x600c -// CHECK-NEXT: 6004: c0 03 5f d6 ret +// CHECK-NEXT: 5ff8: b0000000 adrp x0, 0x6000 +// CHECK-NEXT: 5ffc: f9000021 str x1, [x1] +// CHECK-NEXT: 6000: 14000003 b 0x600c +// CHECK-NEXT: 6004: d65f03c0 ret .section .newos, "ax", %progbits .globl t3_ff8_str @@ -173,8 +173,8 @@ _start: ret // CHECK: <__CortexA53843419_6000>: -// CHECK-NEXT: 600c: 00 0c 40 f9 ldr x0, [x0, #24] -// CHECK-NEXT: 6010: fd ff ff 17 b 0x6004 +// CHECK-NEXT: 600c: f9400c00 ldr x0, [x0, #24] +// CHECK-NEXT: 6010: 17fffffd b 0x6004 .data .globl dat diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-large.s b/lld/test/ELF/aarch64-cortex-a53-843419-large.s index e4b0c0f..bdf95af 100644 --- a/lld/test/ELF/aarch64-cortex-a53-843419-large.s +++ b/lld/test/ELF/aarch64-cortex-a53-843419-large.s @@ -14,8 +14,8 @@ // required. // CHECK1: <__AArch64AbsLongThunk_need_thunk_after_patch>: -// CHECK1-NEXT: 210000: 50 00 00 58 ldr x16, 0x210008 -// CHECK1-NEXT: 210004: 00 02 1f d6 br x16 +// CHECK1-NEXT: 210000: 58000050 ldr x16, 0x210008 +// CHECK1-NEXT: 210004: d61f0200 br x16 // CHECK1: <$d>: // CHECK1-NEXT: 210008: 0c 10 21 08 .word 0x0821100c @@ -30,7 +30,7 @@ _start: .space 4096 - 12 // CHECK2: <_start>: -// CHECK2-NEXT: 211000: 00 fc ff 97 bl 0x210000 +// CHECK2-NEXT: 211000: 97fffc00 bl 0x210000 // Expect patch on pass 1 .section .text.03, "ax", %progbits @@ -43,10 +43,10 @@ t3_ff8_ldr: ret // CHECK3: <t3_ff8_ldr>: -// CHECK3-NEXT: 211ff8: e0 00 04 f0 adrp x0, 0x8230000 -// CHECK3-NEXT: 211ffc: 21 00 40 f9 ldr x1, [x1] -// CHECK3-NEXT: 212000: 02 08 80 15 b 0x6214008 -// CHECK3-NEXT: 212004: c0 03 5f d6 ret +// CHECK3-NEXT: 211ff8: f00400e0 adrp x0, 0x8230000 +// CHECK3-NEXT: 211ffc: f9400021 ldr x1, [x1] +// CHECK3-NEXT: 212000: 15800802 b 0x6214008 +// CHECK3-NEXT: 212004: d65f03c0 ret .section .text.04, "ax", %progbits .space 64 * 1024 * 1024 @@ -64,20 +64,20 @@ t3_ff8_str: ret // CHECK4: <t3_ff8_str>: -// CHECK4-NEXT: 4213ff8: e0 00 02 b0 adrp x0, 0x8230000 -// CHECK4-NEXT: 4213ffc: 21 00 40 f9 ldr x1, [x1] -// CHECK4-NEXT: 4214000: 04 00 80 14 b 0x6214010 -// CHECK4-NEXT: 4214004: c0 03 5f d6 ret +// CHECK4-NEXT: 4213ff8: b00200e0 adrp x0, 0x8230000 +// CHECK4-NEXT: 4213ffc: f9400021 ldr x1, [x1] +// CHECK4-NEXT: 4214000: 14800004 b 0x6214010 +// CHECK4-NEXT: 4214004: d65f03c0 ret .section .text.06, "ax", %progbits .space 32 * 1024 * 1024 // CHECK5: <__CortexA53843419_211000>: -// CHECK5-NEXT: 6214008: 00 00 40 f9 ldr x0, [x0] -// CHECK5-NEXT: 621400c: fe f7 7f 16 b 0x212004 +// CHECK5-NEXT: 6214008: f9400000 ldr x0, [x0] +// CHECK5-NEXT: 621400c: 167ff7fe b 0x212004 // CHECK5: <__CortexA53843419_4213000>: -// CHECK5-NEXT: 6214010: 00 00 00 f9 str x0, [x0] -// CHECK5-NEXT: 6214014: fc ff 7f 17 b 0x4214004 +// CHECK5-NEXT: 6214010: f9000000 str x0, [x0] +// CHECK5-NEXT: 6214014: 177ffffc b 0x4214004 .section .text.07, "ax", %progbits .space (32 * 1024 * 1024) - 12300 @@ -89,7 +89,7 @@ need_thunk_after_patch: ret // CHECK6: <need_thunk_after_patch>: -// CHECK6-NEXT: 821100c: c0 03 5f d6 ret +// CHECK6-NEXT: 821100c: d65f03c0 ret // Will need a patch on pass 2 .section .text.09, "ax", %progbits @@ -103,13 +103,13 @@ t3_ffc_ldr: ret // CHECK7: <t3_ffc_ldr>: -// CHECK7-NEXT: 8211ffc: e0 00 00 f0 adrp x0, 0x8230000 -// CHECK7-NEXT: 8212000: 21 00 40 f9 ldr x1, [x1] -// CHECK7-NEXT: 8212004: 02 00 00 14 b 0x821200c -// CHECK7-NEXT: 8212008: c0 03 5f d6 ret +// CHECK7-NEXT: 8211ffc: f00000e0 adrp x0, 0x8230000 +// CHECK7-NEXT: 8212000: f9400021 ldr x1, [x1] +// CHECK7-NEXT: 8212004: 14000002 b 0x821200c +// CHECK7-NEXT: 8212008: d65f03c0 ret // CHECK7: <__CortexA53843419_8212004>: -// CHECK7-NEXT: 821200c: 00 00 40 f9 ldr x0, [x0] -// CHECK7-NEXT: 8212010: fe ff ff 17 b 0x8212008 +// CHECK7-NEXT: 821200c: f9400000 ldr x0, [x0] +// CHECK7-NEXT: 8212010: 17fffffe b 0x8212008 .section .data .globl dat diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-recognize.s b/lld/test/ELF/aarch64-cortex-a53-843419-recognize.s index 4ad005d..cedb7ca 100644 --- a/lld/test/ELF/aarch64-cortex-a53-843419-recognize.s +++ b/lld/test/ELF/aarch64-cortex-a53-843419-recognize.s @@ -30,16 +30,16 @@ // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 211FF8 in unpatched output. // CHECK: <t3_ff8_ldr>: -// CHECK-NEXT: 211ff8: 60 02 00 f0 adrp x0, 0x260000 -// CHECK-NEXT: 211ffc: 21 00 40 f9 ldr x1, [x1] -// CHECK-FIX: 212000: 03 c8 00 14 b 0x24400c -// CHECK-NOFIX: 212000: 00 00 40 f9 ldr x0, [x0] -// CHECK-NEXT: 212004: c0 03 5f d6 ret +// CHECK-NEXT: 211ff8: f0000260 adrp x0, 0x260000 +// CHECK-NEXT: 211ffc: f9400021 ldr x1, [x1] +// CHECK-FIX: 212000: 1400c803 b 0x24400c +// CHECK-NOFIX: 212000: f9400000 ldr x0, [x0] +// CHECK-NEXT: 212004: d65f03c0 ret // CHECK-RELOCATABLE: <t3_ff8_ldr>: -// CHECK-RELOCATABLE-NEXT: ff8: 00 00 00 90 adrp x0, 0x0 -// CHECK-RELOCATABLE-NEXT: ffc: 21 00 40 f9 ldr x1, [x1] -// CHECK-RELOCATABLE-NEXT: 1000: 00 00 40 f9 ldr x0, [x0] -// CHECK-RELOCATABLE-NEXT: 1004: c0 03 5f d6 ret +// CHECK-RELOCATABLE-NEXT: ff8: 90000000 adrp x0, 0x0 +// CHECK-RELOCATABLE-NEXT: ffc: f9400021 ldr x1, [x1] +// CHECK-RELOCATABLE-NEXT: 1000: f9400000 ldr x0, [x0] +// CHECK-RELOCATABLE-NEXT: 1004: d65f03c0 ret .section .text.01, "ax", %progbits .balign 4096 @@ -54,11 +54,11 @@ t3_ff8_ldr: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 213FF8 in unpatched output. // CHECK: <t3_ff8_ldrsimd>: -// CHECK-NEXT: 213ff8: 60 02 00 b0 adrp x0, 0x260000 -// CHECK-NEXT: 213ffc: 21 00 40 bd ldr s1, [x1] -// CHECK-FIX: 214000: 05 c0 00 14 b 0x244014 -// CHECK-NOFIX: 214000: 02 04 40 f9 ldr x2, [x0, #8] -// CHECK-NEXT: 214004: c0 03 5f d6 ret +// CHECK-NEXT: 213ff8: b0000260 adrp x0, 0x260000 +// CHECK-NEXT: 213ffc: bd400021 ldr s1, [x1] +// CHECK-FIX: 214000: 1400c005 b 0x244014 +// CHECK-NOFIX: 214000: f9400402 ldr x2, [x0, #8] +// CHECK-NEXT: 214004: d65f03c0 ret .section .text.02, "ax", %progbits .balign 4096 .globl t3_ff8_ldrsimd @@ -72,11 +72,11 @@ t3_ff8_ldrsimd: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 215FFC in unpatched output. // CHECK: <t3_ffc_ldrpost>: -// CHECK-NEXT: 215ffc: 40 02 00 f0 adrp x0, 0x260000 -// CHECK-NEXT: 216000: 21 84 40 bc ldr s1, [x1], #8 -// CHECK-FIX: 216004: 06 b8 00 14 b 0x24401c -// CHECK-NOFIX: 216004: 03 08 40 f9 ldr x3, [x0, #16] -// CHECK-NEXT: 216008: c0 03 5f d6 ret +// CHECK-NEXT: 215ffc: f0000240 adrp x0, 0x260000 +// CHECK-NEXT: 216000: bc408421 ldr s1, [x1], #8 +// CHECK-FIX: 216004: 1400b806 b 0x24401c +// CHECK-NOFIX: 216004: f9400803 ldr x3, [x0, #16] +// CHECK-NEXT: 216008: d65f03c0 ret .section .text.03, "ax", %progbits .balign 4096 .globl t3_ffc_ldrpost @@ -90,11 +90,11 @@ t3_ffc_ldrpost: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 217FF8 in unpatched output. // CHECK: <t3_ff8_strpre>: -// CHECK-NEXT: 217ff8: 40 02 00 b0 adrp x0, 0x260000 -// CHECK-NEXT: 217ffc: 21 8c 00 bc str s1, [x1, #8]! -// CHECK-FIX: 218000: 09 b0 00 14 b 0x244024 -// CHECK-NOFIX: 218000: 02 0c 40 f9 ldr x2, [x0, #24] -// CHECK-NEXT: 218004: c0 03 5f d6 ret +// CHECK-NEXT: 217ff8: b0000240 adrp x0, 0x260000 +// CHECK-NEXT: 217ffc: bc008c21 str s1, [x1, #8]! +// CHECK-FIX: 218000: 1400b009 b 0x244024 +// CHECK-NOFIX: 218000: f9400c02 ldr x2, [x0, #24] +// CHECK-NEXT: 218004: d65f03c0 ret .section .text.04, "ax", %progbits .balign 4096 .globl t3_ff8_strpre @@ -108,11 +108,11 @@ t3_ff8_strpre: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 219FFC in unpatched output. // CHECK: <t3_ffc_str>: -// CHECK-NEXT: 219ffc: 3c 02 00 f0 adrp x28, 0x260000 -// CHECK-NEXT: 21a000: 42 00 00 f9 str x2, [x2] -// CHECK-FIX: 21a004: 0a a8 00 14 b 0x24402c -// CHECK-NOFIX: 21a004: 9c 13 00 f9 str x28, [x28, #32] -// CHECK-NEXT: 21a008: c0 03 5f d6 ret +// CHECK-NEXT: 219ffc: f000023c adrp x28, 0x260000 +// CHECK-NEXT: 21a000: f9000042 str x2, [x2] +// CHECK-FIX: 21a004: 1400a80a b 0x24402c +// CHECK-NOFIX: 21a004: f900139c str x28, [x28, #32] +// CHECK-NEXT: 21a008: d65f03c0 ret .section .text.05, "ax", %progbits .balign 4096 .globl t3_ffc_str @@ -126,11 +126,11 @@ t3_ffc_str: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21BFFC in unpatched output. // CHECK: <t3_ffc_strsimd>: -// CHECK-NEXT: 21bffc: 3c 02 00 b0 adrp x28, 0x260000 -// CHECK-NEXT: 21c000: 44 00 00 b9 str w4, [x2] -// CHECK-FIX: 21c004: 0c a0 00 14 b 0x244034 -// CHECK-NOFIX: 21c004: 84 17 00 f9 str x4, [x28, #40] -// CHECK-NEXT: 21c008: c0 03 5f d6 ret +// CHECK-NEXT: 21bffc: b000023c adrp x28, 0x260000 +// CHECK-NEXT: 21c000: b9000044 str w4, [x2] +// CHECK-FIX: 21c004: 1400a00c b 0x244034 +// CHECK-NOFIX: 21c004: f9001784 str x4, [x28, #40] +// CHECK-NEXT: 21c008: d65f03c0 ret .section .text.06, "ax", %progbits .balign 4096 .globl t3_ffc_strsimd @@ -144,11 +144,11 @@ t3_ffc_strsimd: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21DFF8 in unpatched output. // CHECK: <t3_ff8_ldrunpriv>: -// CHECK-NEXT: 21dff8: 1d 02 00 f0 adrp x29, 0x260000 -// CHECK-NEXT: 21dffc: 41 08 40 38 ldtrb w1, [x2] -// CHECK-FIX: 21e000: 0f 98 00 14 b 0x24403c -// CHECK-NOFIX: 21e000: bd 03 40 f9 ldr x29, [x29] -// CHECK-NEXT: 21e004: c0 03 5f d6 ret +// CHECK-NEXT: 21dff8: f000021d adrp x29, 0x260000 +// CHECK-NEXT: 21dffc: 38400841 ldtrb w1, [x2] +// CHECK-FIX: 21e000: 1400980f b 0x24403c +// CHECK-NOFIX: 21e000: f94003bd ldr x29, [x29] +// CHECK-NEXT: 21e004: d65f03c0 ret .section .text.07, "ax", %progbits .balign 4096 .globl t3_ff8_ldrunpriv @@ -162,11 +162,11 @@ t3_ff8_ldrunpriv: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21FFFC in unpatched output. // CHECK: <t3_ffc_ldur>: -// CHECK-NEXT: 21fffc: 1d 02 00 b0 adrp x29, 0x260000 -// CHECK-NEXT: 220000: 42 40 40 b8 ldur w2, [x2, #4] -// CHECK-FIX: 220004: 10 90 00 14 b 0x244044 -// CHECK-NOFIX: 220004: bd 07 40 f9 ldr x29, [x29, #8] -// CHECK-NEXT: 220008: c0 03 5f d6 ret +// CHECK-NEXT: 21fffc: b000021d adrp x29, 0x260000 +// CHECK-NEXT: 220000: b8404042 ldur w2, [x2, #4] +// CHECK-FIX: 220004: 14009010 b 0x244044 +// CHECK-NOFIX: 220004: f94007bd ldr x29, [x29, #8] +// CHECK-NEXT: 220008: d65f03c0 ret .balign 4096 .globl t3_ffc_ldur .type t3_ffc_ldur, %function @@ -179,11 +179,11 @@ t3_ffc_ldur: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 221FFC in unpatched output. // CHECK: <t3_ffc_sturh>: -// CHECK-NEXT: 221ffc: f2 01 00 f0 adrp x18, 0x260000 -// CHECK-NEXT: 222000: 43 40 00 78 sturh w3, [x2, #4] -// CHECK-FIX: 222004: 12 88 00 14 b 0x24404c -// CHECK-NOFIX: 222004: 41 0a 40 f9 ldr x1, [x18, #16] -// CHECK-NEXT: 222008: c0 03 5f d6 ret +// CHECK-NEXT: 221ffc: f00001f2 adrp x18, 0x260000 +// CHECK-NEXT: 222000: 78004043 sturh w3, [x2, #4] +// CHECK-FIX: 222004: 14008812 b 0x24404c +// CHECK-NOFIX: 222004: f9400a41 ldr x1, [x18, #16] +// CHECK-NEXT: 222008: d65f03c0 ret .section .text.09, "ax", %progbits .balign 4096 .globl t3_ffc_sturh @@ -197,11 +197,11 @@ t3_ffc_sturh: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 223FF8 in unpatched output. // CHECK: <t3_ff8_literal>: -// CHECK-NEXT: 223ff8: f2 01 00 b0 adrp x18, 0x260000 -// CHECK-NEXT: 223ffc: e3 ff ff 58 ldr x3, 0x223ff8 -// CHECK-FIX: 224000: 15 80 00 14 b 0x244054 -// CHECK-NOFIX: 224000: 52 0e 40 f9 ldr x18, [x18, #24] -// CHECK-NEXT: 224004: c0 03 5f d6 ret +// CHECK-NEXT: 223ff8: b00001f2 adrp x18, 0x260000 +// CHECK-NEXT: 223ffc: 58ffffe3 ldr x3, 0x223ff8 +// CHECK-FIX: 224000: 14008015 b 0x244054 +// CHECK-NOFIX: 224000: f9400e52 ldr x18, [x18, #24] +// CHECK-NEXT: 224004: d65f03c0 ret .section .text.10, "ax", %progbits .balign 4096 .globl t3_ff8_literal @@ -215,11 +215,11 @@ t3_ff8_literal: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 225FFC in unpatched output. // CHECK: <t3_ffc_register>: -// CHECK-NEXT: 225ffc: cf 01 00 f0 adrp x15, 0x260000 -// CHECK-NEXT: 226000: 43 68 61 f8 ldr x3, [x2, x1] -// CHECK-FIX: 226004: 16 78 00 14 b 0x24405c -// CHECK-NOFIX: 226004: ea 11 40 f9 ldr x10, [x15, #32] -// CHECK-NEXT: 226008: c0 03 5f d6 ret +// CHECK-NEXT: 225ffc: f00001cf adrp x15, 0x260000 +// CHECK-NEXT: 226000: f8616843 ldr x3, [x2, x1] +// CHECK-FIX: 226004: 14007816 b 0x24405c +// CHECK-NOFIX: 226004: f94011ea ldr x10, [x15, #32] +// CHECK-NEXT: 226008: d65f03c0 ret .section .text.11, "ax", %progbits .balign 4096 .globl t3_ffc_register @@ -233,11 +233,11 @@ t3_ffc_register: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 227FF8 in unpatched output. // CHECK: <t3_ff8_stp>: -// CHECK-NEXT: 227ff8: d0 01 00 b0 adrp x16, 0x260000 -// CHECK-NEXT: 227ffc: 61 08 00 a9 stp x1, x2, [x3] -// CHECK-FIX: 228000: 19 70 00 14 b 0x244064 -// CHECK-NOFIX: 228000: 0d 16 40 f9 ldr x13, [x16, #40] -// CHECK-NEXT: 228004: c0 03 5f d6 ret +// CHECK-NEXT: 227ff8: b00001d0 adrp x16, 0x260000 +// CHECK-NEXT: 227ffc: a9000861 stp x1, x2, [x3] +// CHECK-FIX: 228000: 14007019 b 0x244064 +// CHECK-NOFIX: 228000: f940160d ldr x13, [x16, #40] +// CHECK-NEXT: 228004: d65f03c0 ret .section .text.12, "ax", %progbits .balign 4096 .globl t3_ff8_stp @@ -251,11 +251,11 @@ t3_ff8_stp: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 229FFC in unpatched output. // CHECK: <t3_ffc_stnp>: -// CHECK-NEXT: 229ffc: a7 01 00 f0 adrp x7, 0x260000 -// CHECK-NEXT: 22a000: 61 08 00 a8 stnp x1, x2, [x3] -// CHECK-FIX: 22a004: 1a 68 00 14 b 0x24406c -// CHECK-NOFIX: 22a004: e9 0c 40 f9 ldr x9, [x7, #24] -// CHECK-NEXT: 22a008: c0 03 5f d6 ret +// CHECK-NEXT: 229ffc: f00001a7 adrp x7, 0x260000 +// CHECK-NEXT: 22a000: a8000861 stnp x1, x2, [x3] +// CHECK-FIX: 22a004: 1400681a b 0x24406c +// CHECK-NOFIX: 22a004: f9400ce9 ldr x9, [x7, #24] +// CHECK-NEXT: 22a008: d65f03c0 ret .section .text.13, "ax", %progbits .balign 4096 .globl t3_ffc_stnp @@ -269,11 +269,11 @@ t3_ffc_stnp: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22BFFC in unpatched output. // CHECK: <t3_ffc_st1singlepost>: -// CHECK-NEXT: 22bffc: b7 01 00 b0 adrp x23, 0x260000 -// CHECK-NEXT: 22c000: 20 04 82 0d st1 { v0.b }[1], [x1], x2 -// CHECK-FIX: 22c004: 1c 60 00 14 b 0x244074 -// CHECK-NOFIX: 22c004: f6 12 40 f9 ldr x22, [x23, #32] -// CHECK-NEXT: 22c008: c0 03 5f d6 ret +// CHECK-NEXT: 22bffc: b00001b7 adrp x23, 0x260000 +// CHECK-NEXT: 22c000: 0d820420 st1 { v0.b }[1], [x1], x2 +// CHECK-FIX: 22c004: 1400601c b 0x244074 +// CHECK-NOFIX: 22c004: f94012f6 ldr x22, [x23, #32] +// CHECK-NEXT: 22c008: d65f03c0 ret .section .text.14, "ax", %progbits .balign 4096 .globl t3_ffc_st1singlepost @@ -287,11 +287,11 @@ t3_ffc_st1singlepost: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22DFF8 in unpatched output. // CHECK: <t3_ff8_st1multiple>: -// CHECK-NEXT: 22dff8: 97 01 00 f0 adrp x23, 0x260000 -// CHECK-NEXT: 22dffc: 20 a0 00 4c st1 { v0.16b, v1.16b }, [x1] -// CHECK-FIX: 22e000: 1f 58 00 14 b 0x24407c -// CHECK-NOFIX: 22e000: f8 16 40 f9 ldr x24, [x23, #40] -// CHECK-NEXT: 22e004: c0 03 5f d6 ret +// CHECK-NEXT: 22dff8: f0000197 adrp x23, 0x260000 +// CHECK-NEXT: 22dffc: 4c00a020 st1 { v0.16b, v1.16b }, [x1] +// CHECK-FIX: 22e000: 1400581f b 0x24407c +// CHECK-NOFIX: 22e000: f94016f8 ldr x24, [x23, #40] +// CHECK-NEXT: 22e004: d65f03c0 ret .section .text.15, "ax", %progbits .balign 4096 .globl t3_ff8_st1multiple @@ -305,12 +305,12 @@ t3_ff8_st1multiple: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22FFF8 in unpatched output. // CHECK: <t4_ff8_ldr>: -// CHECK-NEXT: 22fff8: 80 01 00 b0 adrp x0, 0x260000 -// CHECK-NEXT: 22fffc: 21 00 40 f9 ldr x1, [x1] -// CHECK-NEXT: 230000: 42 00 00 8b add x2, x2, x0 -// CHECK-FIX: 230004: 20 50 00 14 b 0x244084 -// CHECK-NOFIX: 230004: 02 00 40 f9 ldr x2, [x0] -// CHECK-NEXT: 230008: c0 03 5f d6 ret +// CHECK-NEXT: 22fff8: b0000180 adrp x0, 0x260000 +// CHECK-NEXT: 22fffc: f9400021 ldr x1, [x1] +// CHECK-NEXT: 230000: 8b000042 add x2, x2, x0 +// CHECK-FIX: 230004: 14005020 b 0x244084 +// CHECK-NOFIX: 230004: f9400002 ldr x2, [x0] +// CHECK-NEXT: 230008: d65f03c0 ret .section .text.16, "ax", %progbits .balign 4096 .globl t4_ff8_ldr @@ -325,12 +325,12 @@ t4_ff8_ldr: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 231FFC in unpatched output. // CHECK: <t4_ffc_str>: -// CHECK-NEXT: 231ffc: 7c 01 00 f0 adrp x28, 0x260000 -// CHECK-NEXT: 232000: 42 00 00 f9 str x2, [x2] -// CHECK-NEXT: 232004: 20 00 02 cb sub x0, x1, x2 -// CHECK-FIX: 232008: 21 48 00 14 b 0x24408c -// CHECK-NOFIX: 232008: 9b 07 00 f9 str x27, [x28, #8] -// CHECK-NEXT: 23200c: c0 03 5f d6 ret +// CHECK-NEXT: 231ffc: f000017c adrp x28, 0x260000 +// CHECK-NEXT: 232000: f9000042 str x2, [x2] +// CHECK-NEXT: 232004: cb020020 sub x0, x1, x2 +// CHECK-FIX: 232008: 14004821 b 0x24408c +// CHECK-NOFIX: 232008: f900079b str x27, [x28, #8] +// CHECK-NEXT: 23200c: d65f03c0 ret .section .text.17, "ax", %progbits .balign 4096 .globl t4_ffc_str @@ -345,12 +345,12 @@ t4_ffc_str: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 233FF8 in unpatched output. // CHECK: <t4_ff8_stp>: -// CHECK-NEXT: 233ff8: 70 01 00 b0 adrp x16, 0x260000 -// CHECK-NEXT: 233ffc: 61 08 00 a9 stp x1, x2, [x3] -// CHECK-NEXT: 234000: 03 7e 10 9b mul x3, x16, x16 -// CHECK-FIX: 234004: 24 40 00 14 b 0x244094 -// CHECK-NOFIX: 234004: 0e 0a 40 f9 ldr x14, [x16, #16] -// CHECK-NEXT: 234008: c0 03 5f d6 ret +// CHECK-NEXT: 233ff8: b0000170 adrp x16, 0x260000 +// CHECK-NEXT: 233ffc: a9000861 stp x1, x2, [x3] +// CHECK-NEXT: 234000: 9b107e03 mul x3, x16, x16 +// CHECK-FIX: 234004: 14004024 b 0x244094 +// CHECK-NOFIX: 234004: f9400a0e ldr x14, [x16, #16] +// CHECK-NEXT: 234008: d65f03c0 ret .section .text.18, "ax", %progbits .balign 4096 .globl t4_ff8_stp @@ -365,12 +365,12 @@ t4_ff8_stp: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 235FF8 in unpatched output. // CHECK: <t4_ff8_stppre>: -// CHECK-NEXT: 235ff8: 50 01 00 f0 adrp x16, 0x260000 -// CHECK-NEXT: 235ffc: 61 08 81 a9 stp x1, x2, [x3, #16]! -// CHECK-NEXT: 236000: 03 7e 10 9b mul x3, x16, x16 -// CHECK-FIX: 236004: 26 38 00 14 b 0x24409c -// CHECK-NOFIX: 236004: 0e 06 40 f9 ldr x14, [x16, #8] -// CHECK-NEXT: 236008: c0 03 5f d6 ret +// CHECK-NEXT: 235ff8: f0000150 adrp x16, 0x260000 +// CHECK-NEXT: 235ffc: a9810861 stp x1, x2, [x3, #16]! +// CHECK-NEXT: 236000: 9b107e03 mul x3, x16, x16 +// CHECK-FIX: 236004: 14003826 b 0x24409c +// CHECK-NOFIX: 236004: f940060e ldr x14, [x16, #8] +// CHECK-NEXT: 236008: d65f03c0 ret .section .text.19, "ax", %progbits .balign 4096 .globl t4_ff8_stppre @@ -385,12 +385,12 @@ t4_ff8_stppre: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 237FF8 in unpatched output. // CHECK: <t4_ff8_stppost>: -// CHECK-NEXT: 237ff8: 50 01 00 b0 adrp x16, 0x260000 -// CHECK-NEXT: 237ffc: 61 08 81 a8 stp x1, x2, [x3], #16 -// CHECK-NEXT: 238000: 03 7e 10 9b mul x3, x16, x16 -// CHECK-FIX: 238004: 28 30 00 14 b 0x2440a4 -// CHECK-NOFIX: 238004: 0e 06 40 f9 ldr x14, [x16, #8] -// CHECK-NEXT: 238008: c0 03 5f d6 ret +// CHECK-NEXT: 237ff8: b0000150 adrp x16, 0x260000 +// CHECK-NEXT: 237ffc: a8810861 stp x1, x2, [x3], #16 +// CHECK-NEXT: 238000: 9b107e03 mul x3, x16, x16 +// CHECK-FIX: 238004: 14003028 b 0x2440a4 +// CHECK-NOFIX: 238004: f940060e ldr x14, [x16, #8] +// CHECK-NEXT: 238008: d65f03c0 ret .section .text.20, "ax", %progbits .balign 4096 .globl t4_ff8_stppost @@ -405,12 +405,12 @@ t4_ff8_stppost: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 239FFC in unpatched output. // CHECK: <t4_ffc_stpsimd>: -// CHECK-NEXT: 239ffc: 30 01 00 f0 adrp x16, 0x260000 -// CHECK-NEXT: 23a000: 61 08 00 ad stp q1, q2, [x3] -// CHECK-NEXT: 23a004: 03 7e 10 9b mul x3, x16, x16 -// CHECK-FIX: 23a008: 29 28 00 14 b 0x2440ac -// CHECK-NOFIX: 23a008: 0e 06 40 f9 ldr x14, [x16, #8] -// CHECK-NEXT: 23a00c: c0 03 5f d6 ret +// CHECK-NEXT: 239ffc: f0000130 adrp x16, 0x260000 +// CHECK-NEXT: 23a000: ad000861 stp q1, q2, [x3] +// CHECK-NEXT: 23a004: 9b107e03 mul x3, x16, x16 +// CHECK-FIX: 23a008: 14002829 b 0x2440ac +// CHECK-NOFIX: 23a008: f940060e ldr x14, [x16, #8] +// CHECK-NEXT: 23a00c: d65f03c0 ret .section .text.21, "ax", %progbits .balign 4096 .globl t4_ffc_stpsimd @@ -425,12 +425,12 @@ t4_ffc_stpsimd: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23BFFC in unpatched output. // CHECK: <t4_ffc_stnp>: -// CHECK-NEXT: 23bffc: 27 01 00 b0 adrp x7, 0x260000 -// CHECK-NEXT: 23c000: 61 08 00 a8 stnp x1, x2, [x3] -// CHECK-NEXT: 23c004: 1f 20 03 d5 nop -// CHECK-FIX: 23c008: 2b 20 00 14 b 0x2440b4 -// CHECK-NOFIX: 23c008: ea 00 40 f9 ldr x10, [x7] -// CHECK-NEXT: 23c00c: c0 03 5f d6 ret +// CHECK-NEXT: 23bffc: b0000127 adrp x7, 0x260000 +// CHECK-NEXT: 23c000: a8000861 stnp x1, x2, [x3] +// CHECK-NEXT: 23c004: d503201f nop +// CHECK-FIX: 23c008: 1400202b b 0x2440b4 +// CHECK-NOFIX: 23c008: f94000ea ldr x10, [x7] +// CHECK-NEXT: 23c00c: d65f03c0 ret .section .text.22, "ax", %progbits .balign 4096 .globl t4_ffc_stnp @@ -445,12 +445,12 @@ t4_ffc_stnp: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23DFFC in unpatched output. // CHECK: <t4_ffc_st1>: -// CHECK-NEXT: 23dffc: 18 01 00 f0 adrp x24, 0x260000 -// CHECK-NEXT: 23e000: 20 80 00 4d st1 { v0.s }[2], [x1] -// CHECK-NEXT: 23e004: f6 06 40 f9 ldr x22, [x23, #8] -// CHECK-FIX: 23e008: 2d 18 00 14 b 0x2440bc -// CHECK-NOFIX: 23e008: 18 ff 3f f9 str x24, [x24, #32760] -// CHECK-NEXT: 23e00c: c0 03 5f d6 ret +// CHECK-NEXT: 23dffc: f0000118 adrp x24, 0x260000 +// CHECK-NEXT: 23e000: 4d008020 st1 { v0.s }[2], [x1] +// CHECK-NEXT: 23e004: f94006f6 ldr x22, [x23, #8] +// CHECK-FIX: 23e008: 1400182d b 0x2440bc +// CHECK-NOFIX: 23e008: f93fff18 str x24, [x24, #32760] +// CHECK-NEXT: 23e00c: d65f03c0 ret .section .text.23, "ax", %progbits .balign 4096 .globl t4_ffc_st1 @@ -465,12 +465,12 @@ t4_ffc_st1: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23FFF8 in unpatched output. // CHECK: <t3_ff8_ldr_once>: -// CHECK-NEXT: 23fff8: 00 01 00 b0 adrp x0, 0x260000 -// CHECK-NEXT: 23fffc: 20 70 82 4c st1 { v0.16b }, [x1], x2 -// CHECK-FIX: 240000: 31 10 00 14 b 0x2440c4 -// CHECK-NOFIX: 240000: 01 08 40 f9 ldr x1, [x0, #16] -// CHECK-NEXT: 240004: 02 08 40 f9 ldr x2, [x0, #16] -// CHECK-NEXT: 240008: c0 03 5f d6 ret +// CHECK-NEXT: 23fff8: b0000100 adrp x0, 0x260000 +// CHECK-NEXT: 23fffc: 4c827020 st1 { v0.16b }, [x1], x2 +// CHECK-FIX: 240000: 14001031 b 0x2440c4 +// CHECK-NOFIX: 240000: f9400801 ldr x1, [x0, #16] +// CHECK-NEXT: 240004: f9400802 ldr x2, [x0, #16] +// CHECK-NEXT: 240008: d65f03c0 ret .section .text.24, "ax", %progbits .balign 4096 .globl t3_ff8_ldr_once @@ -485,12 +485,12 @@ t3_ff8_ldr_once: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 241FF8 in unpatched output. // CHECK: <t3_ff8_ldxr>: -// CHECK-NEXT: 241ff8: e0 00 00 f0 adrp x0, 0x260000 -// CHECK-NEXT: 241ffc: 03 7c 5f c8 ldxr x3, [x0] -// CHECK-FIX: 242000: 33 08 00 14 b 0x2440cc -// CHECK-NOFIX: 242000: 01 08 40 f9 ldr x1, [x0, #16] -// CHECK: 242004: 02 08 40 f9 ldr x2, [x0, #16] -// CHECK-NEXT: 242008: c0 03 5f d6 ret +// CHECK-NEXT: 241ff8: f00000e0 adrp x0, 0x260000 +// CHECK-NEXT: 241ffc: c85f7c03 ldxr x3, [x0] +// CHECK-FIX: 242000: 14000833 b 0x2440cc +// CHECK-NOFIX: 242000: f9400801 ldr x1, [x0, #16] +// CHECK: 242004: f9400802 ldr x2, [x0, #16] +// CHECK-NEXT: 242008: d65f03c0 ret .section .text.25, "ax", %progbits .balign 4096 .globl t3_ff8_ldxr @@ -505,12 +505,12 @@ t3_ff8_ldxr: // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 243FF8 in unpatched output. // CHECK: <t3_ff8_stxr>: -// CHECK-NEXT: 243ff8: e0 00 00 b0 adrp x0, 0x260000 -// CHECK-NEXT: 243ffc: 03 7c 04 c8 stxr w4, x3, [x0] -// CHECK-FIX: 244000: 35 00 00 14 b 0x2440d4 -// CHECK-NOFIX: 244000: 01 08 40 f9 ldr x1, [x0, #16] -// CHECK: 244004: 02 08 40 f9 ldr x2, [x0, #16] -// CHECK-NEXT: 244008: c0 03 5f d6 ret +// CHECK-NEXT: 243ff8: b00000e0 adrp x0, 0x260000 +// CHECK-NEXT: 243ffc: c8047c03 stxr w4, x3, [x0] +// CHECK-FIX: 244000: 14000035 b 0x2440d4 +// CHECK-NOFIX: 244000: f9400801 ldr x1, [x0, #16] +// CHECK: 244004: f9400802 ldr x2, [x0, #16] +// CHECK-NEXT: 244008: d65f03c0 ret .section .text.26, "ax", %progbits .balign 4096 .globl t3_ff8_stxr @@ -530,83 +530,83 @@ _start: ret // CHECK-FIX: <__CortexA53843419_212000>: -// CHECK-FIX-NEXT: 24400c: 00 00 40 f9 ldr x0, [x0] -// CHECK-FIX-NEXT: 244010: fd 37 ff 17 b 0x212004 +// CHECK-FIX-NEXT: 24400c: f9400000 ldr x0, [x0] +// CHECK-FIX-NEXT: 244010: 17ff37fd b 0x212004 // CHECK-FIX: <__CortexA53843419_214000>: -// CHECK-FIX-NEXT: 244014: 02 04 40 f9 ldr x2, [x0, #8] -// CHECK-FIX-NEXT: 244018: fb 3f ff 17 b 0x214004 +// CHECK-FIX-NEXT: 244014: f9400402 ldr x2, [x0, #8] +// CHECK-FIX-NEXT: 244018: 17ff3ffb b 0x214004 // CHECK-FIX: <__CortexA53843419_216004>: -// CHECK-FIX-NEXT: 24401c: 03 08 40 f9 ldr x3, [x0, #16] -// CHECK-FIX-NEXT: 244020: fa 47 ff 17 b 0x216008 +// CHECK-FIX-NEXT: 24401c: f9400803 ldr x3, [x0, #16] +// CHECK-FIX-NEXT: 244020: 17ff47fa b 0x216008 // CHECK-FIX: <__CortexA53843419_218000>: -// CHECK-FIX-NEXT: 244024: 02 0c 40 f9 ldr x2, [x0, #24] -// CHECK-FIX-NEXT: 244028: f7 4f ff 17 b 0x218004 +// CHECK-FIX-NEXT: 244024: f9400c02 ldr x2, [x0, #24] +// CHECK-FIX-NEXT: 244028: 17ff4ff7 b 0x218004 // CHECK-FIX: <__CortexA53843419_21A004>: -// CHECK-FIX-NEXT: 24402c: 9c 13 00 f9 str x28, [x28, #32] -// CHECK-FIX-NEXT: 244030: f6 57 ff 17 b 0x21a008 +// CHECK-FIX-NEXT: 24402c: f900139c str x28, [x28, #32] +// CHECK-FIX-NEXT: 244030: 17ff57f6 b 0x21a008 // CHECK-FIX: <__CortexA53843419_21C004>: -// CHECK-FIX-NEXT: 244034: 84 17 00 f9 str x4, [x28, #40] -// CHECK-FIX-NEXT: 244038: f4 5f ff 17 b 0x21c008 +// CHECK-FIX-NEXT: 244034: f9001784 str x4, [x28, #40] +// CHECK-FIX-NEXT: 244038: 17ff5ff4 b 0x21c008 // CHECK-FIX: <__CortexA53843419_21E000>: -// CHECK-FIX-NEXT: 24403c: bd 03 40 f9 ldr x29, [x29] -// CHECK-FIX-NEXT: 244040: f1 67 ff 17 b 0x21e004 +// CHECK-FIX-NEXT: 24403c: f94003bd ldr x29, [x29] +// CHECK-FIX-NEXT: 244040: 17ff67f1 b 0x21e004 // CHECK-FIX: <__CortexA53843419_220004>: -// CHECK-FIX-NEXT: 244044: bd 07 40 f9 ldr x29, [x29, #8] -// CHECK-FIX-NEXT: 244048: f0 6f ff 17 b 0x220008 +// CHECK-FIX-NEXT: 244044: f94007bd ldr x29, [x29, #8] +// CHECK-FIX-NEXT: 244048: 17ff6ff0 b 0x220008 // CHECK-FIX: <__CortexA53843419_222004>: -// CHECK-FIX-NEXT: 24404c: 41 0a 40 f9 ldr x1, [x18, #16] -// CHECK-FIX-NEXT: 244050: ee 77 ff 17 b 0x222008 +// CHECK-FIX-NEXT: 24404c: f9400a41 ldr x1, [x18, #16] +// CHECK-FIX-NEXT: 244050: 17ff77ee b 0x222008 // CHECK-FIX: <__CortexA53843419_224000>: -// CHECK-FIX-NEXT: 244054: 52 0e 40 f9 ldr x18, [x18, #24] -// CHECK-FIX-NEXT: 244058: eb 7f ff 17 b 0x224004 +// CHECK-FIX-NEXT: 244054: f9400e52 ldr x18, [x18, #24] +// CHECK-FIX-NEXT: 244058: 17ff7feb b 0x224004 // CHECK-FIX: <__CortexA53843419_226004>: -// CHECK-FIX-NEXT: 24405c: ea 11 40 f9 ldr x10, [x15, #32] -// CHECK-FIX-NEXT: 244060: ea 87 ff 17 b 0x226008 +// CHECK-FIX-NEXT: 24405c: f94011ea ldr x10, [x15, #32] +// CHECK-FIX-NEXT: 244060: 17ff87ea b 0x226008 // CHECK-FIX: <__CortexA53843419_228000>: -// CHECK-FIX-NEXT: 244064: 0d 16 40 f9 ldr x13, [x16, #40] -// CHECK-FIX-NEXT: 244068: e7 8f ff 17 b 0x228004 +// CHECK-FIX-NEXT: 244064: f940160d ldr x13, [x16, #40] +// CHECK-FIX-NEXT: 244068: 17ff8fe7 b 0x228004 // CHECK-FIX: <__CortexA53843419_22A004>: -// CHECK-FIX-NEXT: 24406c: e9 0c 40 f9 ldr x9, [x7, #24] -// CHECK-FIX-NEXT: 244070: e6 97 ff 17 b 0x22a008 +// CHECK-FIX-NEXT: 24406c: f9400ce9 ldr x9, [x7, #24] +// CHECK-FIX-NEXT: 244070: 17ff97e6 b 0x22a008 // CHECK-FIX: <__CortexA53843419_22C004>: -// CHECK-FIX-NEXT: 244074: f6 12 40 f9 ldr x22, [x23, #32] -// CHECK-FIX-NEXT: 244078: e4 9f ff 17 b 0x22c008 +// CHECK-FIX-NEXT: 244074: f94012f6 ldr x22, [x23, #32] +// CHECK-FIX-NEXT: 244078: 17ff9fe4 b 0x22c008 // CHECK-FIX: <__CortexA53843419_22E000>: -// CHECK-FIX-NEXT: 24407c: f8 16 40 f9 ldr x24, [x23, #40] -// CHECK-FIX-NEXT: 244080: e1 a7 ff 17 b 0x22e004 +// CHECK-FIX-NEXT: 24407c: f94016f8 ldr x24, [x23, #40] +// CHECK-FIX-NEXT: 244080: 17ffa7e1 b 0x22e004 // CHECK-FIX: <__CortexA53843419_230004>: -// CHECK-FIX-NEXT: 244084: 02 00 40 f9 ldr x2, [x0] -// CHECK-FIX-NEXT: 244088: e0 af ff 17 b 0x230008 +// CHECK-FIX-NEXT: 244084: f9400002 ldr x2, [x0] +// CHECK-FIX-NEXT: 244088: 17ffafe0 b 0x230008 // CHECK-FIX: <__CortexA53843419_232008>: -// CHECK-FIX-NEXT: 24408c: 9b 07 00 f9 str x27, [x28, #8] -// CHECK-FIX-NEXT: 244090: df b7 ff 17 b 0x23200c +// CHECK-FIX-NEXT: 24408c: f900079b str x27, [x28, #8] +// CHECK-FIX-NEXT: 244090: 17ffb7df b 0x23200c // CHECK-FIX: <__CortexA53843419_234004>: -// CHECK-FIX-NEXT: 244094: 0e 0a 40 f9 ldr x14, [x16, #16] -// CHECK-FIX-NEXT: 244098: dc bf ff 17 b 0x234008 +// CHECK-FIX-NEXT: 244094: f9400a0e ldr x14, [x16, #16] +// CHECK-FIX-NEXT: 244098: 17ffbfdc b 0x234008 // CHECK-FIX: <__CortexA53843419_236004>: -// CHECK-FIX-NEXT: 24409c: 0e 06 40 f9 ldr x14, [x16, #8] -// CHECK-FIX-NEXT: 2440a0: da c7 ff 17 b 0x236008 +// CHECK-FIX-NEXT: 24409c: f940060e ldr x14, [x16, #8] +// CHECK-FIX-NEXT: 2440a0: 17ffc7da b 0x236008 // CHECK-FIX: <__CortexA53843419_238004>: -// CHECK-FIX-NEXT: 2440a4: 0e 06 40 f9 ldr x14, [x16, #8] -// CHECK-FIX-NEXT: 2440a8: d8 cf ff 17 b 0x238008 +// CHECK-FIX-NEXT: 2440a4: f940060e ldr x14, [x16, #8] +// CHECK-FIX-NEXT: 2440a8: 17ffcfd8 b 0x238008 // CHECK-FIX: <__CortexA53843419_23A008>: -// CHECK-FIX-NEXT: 2440ac: 0e 06 40 f9 ldr x14, [x16, #8] -// CHECK-FIX-NEXT: 2440b0: d7 d7 ff 17 b 0x23a00c +// CHECK-FIX-NEXT: 2440ac: f940060e ldr x14, [x16, #8] +// CHECK-FIX-NEXT: 2440b0: 17ffd7d7 b 0x23a00c // CHECK-FIX: <__CortexA53843419_23C008>: -// CHECK-FIX-NEXT: 2440b4: ea 00 40 f9 ldr x10, [x7] -// CHECK-FIX-NEXT: 2440b8: d5 df ff 17 b 0x23c00c +// CHECK-FIX-NEXT: 2440b4: f94000ea ldr x10, [x7] +// CHECK-FIX-NEXT: 2440b8: 17ffdfd5 b 0x23c00c // CHECK-FIX: <__CortexA53843419_23E008>: -// CHECK-FIX-NEXT: 2440bc: 18 ff 3f f9 str x24, [x24, #32760] -// CHECK-FIX-NEXT: 2440c0: d3 e7 ff 17 b 0x23e00c +// CHECK-FIX-NEXT: 2440bc: f93fff18 str x24, [x24, #32760] +// CHECK-FIX-NEXT: 2440c0: 17ffe7d3 b 0x23e00c // CHECK-FIX: <__CortexA53843419_240000>: -// CHECK-FIX-NEXT: 2440c4: 01 08 40 f9 ldr x1, [x0, #16] -// CHECK-FIX-NEXT: 2440c8: cf ef ff 17 b 0x240004 +// CHECK-FIX-NEXT: 2440c4: f9400801 ldr x1, [x0, #16] +// CHECK-FIX-NEXT: 2440c8: 17ffefcf b 0x240004 // CHECK-FIX: <__CortexA53843419_242000>: -// CHECK-FIX-NEXT: 2440cc: 01 08 40 f9 ldr x1, [x0, #16] -// CHECK-FIX-NEXT: 2440d0: cd f7 ff 17 b 0x242004 +// CHECK-FIX-NEXT: 2440cc: f9400801 ldr x1, [x0, #16] +// CHECK-FIX-NEXT: 2440d0: 17fff7cd b 0x242004 // CHECK-FIX: <__CortexA53843419_244000>: -// CHECK-FIX-NEXT: 2440d4: 01 08 40 f9 ldr x1, [x0, #16] -// CHECK-FIX-NEXT: 2440d8: cb ff ff 17 b 0x244004 +// CHECK-FIX-NEXT: 2440d4: f9400801 ldr x1, [x0, #16] +// CHECK-FIX-NEXT: 2440d8: 17ffffcb b 0x244004 .data .globl dat1 .globl dat2 diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s b/lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s index 3be0315..60845ec 100644 --- a/lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s +++ b/lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s @@ -24,12 +24,12 @@ _start: ret // CHECK: <_start>: -// CHECK-NEXT: 211ff8: 41 d0 3b d5 mrs x1, TPIDR_EL0 -// CHECK-NEXT: 211ffc: 00 00 a0 d2 movz x0, #0, lsl #16 -// CHECK-NEXT: 212000: 01 02 80 f2 movk x1, #16 -// CHECK-NEXT: 212004: 00 00 a0 d2 movz x0, #0, lsl #16 -// CHECK-NEXT: 212008: 01 02 80 f2 movk x1, #16 -// CHECK-NEXT: 21200c: c0 03 5f d6 ret +// CHECK-NEXT: 211ff8: d53bd041 mrs x1, TPIDR_EL0 +// CHECK-NEXT: 211ffc: d2a00000 movz x0, #0, lsl #16 +// CHECK-NEXT: 212000: f2800201 movk x1, #16 +// CHECK-NEXT: 212004: d2a00000 movz x0, #0, lsl #16 +// CHECK-NEXT: 212008: f2800201 movk x1, #16 +// CHECK-NEXT: 21200c: d65f03c0 ret .type v,@object .section .tbss,"awT",@nobits diff --git a/lld/test/ELF/aarch64-relocs.s b/lld/test/ELF/aarch64-relocs.s index 0018744..3352e4f 100644 --- a/lld/test/ELF/aarch64-relocs.s +++ b/lld/test/ELF/aarch64-relocs.s @@ -14,7 +14,7 @@ msgend: # CHECK: Disassembly of section .R_AARCH64_ADR_PREL_LO21: # CHECK-EMPTY: # CHECK: <_start>: -# CHECK: 0: 21 00 00 10 adr x1, #4 +# CHECK: 0: 10000021 adr x1, #4 # CHECK: <msg>: # CHECK: 4: # #4 is the adr immediate value. @@ -30,7 +30,7 @@ mystr: # CHECK: Disassembly of section .R_AARCH64_ADR_PREL_PG_HI21: # CHECK-EMPTY: # CHECK-NEXT: <$x.2>: -# CHECK-NEXT: 210132: 01 00 00 90 adrp x1, 0x210000 +# CHECK-NEXT: 210132: 90000001 adrp x1, 0x210000 .section .R_AARCH64_ADD_ABS_LO12_NC,"ax",@progbits add x0, x0, :lo12:.L.str @@ -44,7 +44,7 @@ mystr: # CHECK: Disassembly of section .R_AARCH64_ADD_ABS_LO12_NC: # CHECK-EMPTY: # CHECK-NEXT: <$x.4>: -# CHECK-NEXT: 21013b: 00 fc 04 91 add x0, x0, #319 +# CHECK-NEXT: 21013b: 9104fc00 add x0, x0, #319 .section .R_AARCH64_LDST64_ABS_LO12_NC,"ax",@progbits ldr x28, [x27, :lo12:foo] @@ -58,7 +58,7 @@ foo: # CHECK: Disassembly of section .R_AARCH64_LDST64_ABS_LO12_NC: # CHECK-EMPTY: # CHECK-NEXT: <$x.6>: -# CHECK-NEXT: 210144: 7c a7 40 f9 ldr x28, [x27, #328] +# CHECK-NEXT: 210144: f940a77c ldr x28, [x27, #328] .section .SUB,"ax",@progbits nop @@ -68,9 +68,9 @@ sub: # CHECK: Disassembly of section .SUB: # CHECK-EMPTY: # CHECK-NEXT: <$x.8>: -# CHECK-NEXT: 21014c: 1f 20 03 d5 nop +# CHECK-NEXT: 21014c: d503201f nop # CHECK: <sub>: -# CHECK-NEXT: 210150: 1f 20 03 d5 nop +# CHECK-NEXT: 210150: d503201f nop .section .R_AARCH64_CALL26,"ax",@progbits call26: @@ -83,7 +83,7 @@ call26: # CHECK: Disassembly of section .R_AARCH64_CALL26: # CHECK-EMPTY: # CHECK-NEXT: <call26>: -# CHECK-NEXT: 210154: ff ff ff 97 bl 0x210150 +# CHECK-NEXT: 210154: 97ffffff bl 0x210150 .section .R_AARCH64_JUMP26,"ax",@progbits jump26: @@ -96,7 +96,7 @@ jump26: # CHECK: Disassembly of section .R_AARCH64_JUMP26: # CHECK-EMPTY: # CHECK-NEXT: <jump26>: -# CHECK-NEXT: 210158: fe ff ff 17 b 0x210150 +# CHECK-NEXT: 210158: 17fffffe b 0x210150 .section .R_AARCH64_LDST32_ABS_LO12_NC,"ax",@progbits ldst32: @@ -111,7 +111,7 @@ foo32: # CHECK: Disassembly of section .R_AARCH64_LDST32_ABS_LO12_NC: # CHECK-EMPTY: # CHECK-NEXT: <ldst32>: -# CHECK-NEXT: 21015c: a4 60 41 bd ldr s4, [x5, #352] +# CHECK-NEXT: 21015c: bd4160a4 ldr s4, [x5, #352] .section .R_AARCH64_LDST8_ABS_LO12_NC,"ax",@progbits ldst8: @@ -126,7 +126,7 @@ foo8: # CHECK: Disassembly of section .R_AARCH64_LDST8_ABS_LO12_NC: # CHECK-EMPTY: # CHECK-NEXT: <ldst8>: -# CHECK-NEXT: 210164: ab a1 85 39 ldrsb x11, [x13, #360] +# CHECK-NEXT: 210164: 3985a1ab ldrsb x11, [x13, #360] .section .R_AARCH64_LDST128_ABS_LO12_NC,"ax",@progbits ldst128: @@ -141,7 +141,7 @@ foo128: # CHECK: Disassembly of section .R_AARCH64_LDST128_ABS_LO12_NC: # CHECK-EMPTY: # CHECK: <ldst128>: -# CHECK: 21016c: 74 5e c0 3d ldr q20, [x19, #368] +# CHECK: 21016c: 3dc05e74 ldr q20, [x19, #368] #foo128: # 210170: 66 6f 6f 00 .word @@ -160,9 +160,9 @@ foo16: # CHECK: Disassembly of section .R_AARCH64_LDST16_ABS_LO12_NC: # CHECK-EMPTY: # CHECK-NEXT: <ldst16>: -# CHECK-NEXT: 210174: 71 02 43 7d ldr h17, [x19, #384] -# CHECK-NEXT: 210178: 61 02 43 79 ldrh w1, [x19, #384] -# CHECK-NEXT: 21017c: 62 06 43 79 ldrh w2, [x19, #386] +# CHECK-NEXT: 210174: 7d430271 ldr h17, [x19, #384] +# CHECK-NEXT: 210178: 79430261 ldrh w1, [x19, #384] +# CHECK-NEXT: 21017c: 79430662 ldrh w2, [x19, #386] .section .R_AARCH64_MOVW_UABS,"ax",@progbits movz1: @@ -179,14 +179,14 @@ movz1: # CHECK: Disassembly of section .R_AARCH64_MOVW_UABS: # CHECK-EMPTY: # CHECK-NEXT: <movz1>: -# CHECK-NEXT: 8c 01 80 f2 movk x12, #12 -# CHECK-NEXT: 8c 01 80 f2 movk x12, #12 -# CHECK-NEXT: ad 01 a0 f2 movk x13, #13, lsl #16 -# CHECK-NEXT: ad 01 a0 f2 movk x13, #13, lsl #16 -# CHECK-NEXT: ce 01 c0 f2 movk x14, #14, lsl #32 -# CHECK-NEXT: ce 01 c0 f2 movk x14, #14, lsl #32 -# CHECK-NEXT: ef 01 e0 d2 mov x15, #4222124650659840 -# CHECK-NEXT: f0 01 e0 f2 movk x16, #15, lsl #48 +# CHECK-NEXT: f280018c movk x12, #12 +# CHECK-NEXT: f280018c movk x12, #12 +# CHECK-NEXT: f2a001ad movk x13, #13, lsl #16 +# CHECK-NEXT: f2a001ad movk x13, #13, lsl #16 +# CHECK-NEXT: f2c001ce movk x14, #14, lsl #32 +# CHECK-NEXT: f2c001ce movk x14, #14, lsl #32 +# CHECK-NEXT: d2e001ef mov x15, #4222124650659840 +# CHECK-NEXT: f2e001f0 movk x16, #15, lsl #48 .section .R_AARCH64_MOVW_SABS,"ax",@progbits movz x1, #:abs_g0_s:zero+1 @@ -199,15 +199,15 @@ movz1: # CHECK: Disassembly of section .R_AARCH64_MOVW_SABS: # CHECK-EMPTY: # CHECK-NEXT: : -# CHECK-NEXT: 21 00 80 d2 mov x1, #1 -# CHECK-NEXT: 01 00 80 92 mov x1, #-1 -# CHECK-NEXT: 42 00 a0 d2 mov x2, #131072 +# CHECK-NEXT: d2800021 mov x1, #1 +# CHECK-NEXT: 92800001 mov x1, #-1 +# CHECK-NEXT: d2a00042 mov x2, #131072 ## -65537 = 0xfffffffffffeffff -# CHECK-NEXT: 22 00 a0 92 mov x2, #-65537 +# CHECK-NEXT: 92a00022 mov x2, #-65537 ## 12884901888 = 0x300000000 -# CHECK-NEXT: 63 00 c0 d2 mov x3, #12884901888 +# CHECK-NEXT: d2c00063 mov x3, #12884901888 ## -8589934593 = #0xfffffffdffffffff -# CHECK-NEXT: 43 00 c0 92 mov x3, #-8589934593 +# CHECK-NEXT: 92c00043 mov x3, #-8589934593 .section .R_AARCH64_MOVW_PREL,"ax",@progbits movz x1, #:prel_g0:.+1 @@ -231,24 +231,24 @@ movz1: # CHECK: Disassembly of section .R_AARCH64_MOVW_PREL: # CHECK-EMPTY: # CHECK-NEXT: : -# CHECK-NEXT: 2101bc: 21 00 80 d2 mov x1, #1 -# CHECK-NEXT: 2101c0: 01 00 80 92 mov x1, #-1 -# CHECK-NEXT: 2101c4: 21 00 80 f2 movk x1, #1 -# CHECK-NEXT: 2101c8: e1 ff 9f f2 movk x1, #65535 -# CHECK-NEXT: 2101cc: 42 00 a0 d2 mov x2, #131072 +# CHECK-NEXT: 2101bc: d2800021 mov x1, #1 +# CHECK-NEXT: 2101c0: 92800001 mov x1, #-1 +# CHECK-NEXT: 2101c4: f2800021 movk x1, #1 +# CHECK-NEXT: 2101c8: f29fffe1 movk x1, #65535 +# CHECK-NEXT: 2101cc: d2a00042 mov x2, #131072 ## -65537 = 0xfffffffffffeffff -# CHECK-NEXT: 2101d0: 22 00 a0 92 mov x2, #-65537 -# CHECK-NEXT: 2101d4: 42 00 a0 f2 movk x2, #2, lsl #16 -# CHECK-NEXT: 2101d8: c2 ff bf f2 movk x2, #65534, lsl #16 +# CHECK-NEXT: 2101d0: 92a00022 mov x2, #-65537 +# CHECK-NEXT: 2101d4: f2a00042 movk x2, #2, lsl #16 +# CHECK-NEXT: 2101d8: f2bfffc2 movk x2, #65534, lsl #16 ## 12884901888 = 0x300000000 -# CHECK-NEXT: 2101dc: 63 00 c0 d2 mov x3, #12884901888 +# CHECK-NEXT: 2101dc: d2c00063 mov x3, #12884901888 ## -8589934593 = #0xfffffffdffffffff -# CHECK-NEXT: 2101e0: 43 00 c0 92 mov x3, #-8589934593 -# CHECK-NEXT: 2101e4: 63 00 c0 f2 movk x3, #3, lsl #32 -# CHECK-NEXT: 2101e8: a3 ff df f2 movk x3, #65533, lsl #32 -# CHECK-NEXT: 2101ec: 63 00 c0 d2 mov x3, #12884901888 +# CHECK-NEXT: 2101e0: 92c00043 mov x3, #-8589934593 +# CHECK-NEXT: 2101e4: f2c00063 movk x3, #3, lsl #32 +# CHECK-NEXT: 2101e8: f2dfffa3 movk x3, #65533, lsl #32 +# CHECK-NEXT: 2101ec: d2c00063 mov x3, #12884901888 ## 1125899906842624 = 0x4000000000000 -# CHECK-NEXT: 2101f0: 84 00 e0 d2 mov x4, #1125899906842624 -# CHECK-NEXT: 2101f4: 84 ff ff d2 mov x4, #-1125899906842624 -# CHECK-NEXT: 2101f8: 84 00 e0 f2 movk x4, #4, lsl #48 -# CHECK-NEXT: 2101fc: 84 ff ff f2 movk x4, #65532, lsl #48 +# CHECK-NEXT: 2101f0: d2e00084 mov x4, #1125899906842624 +# CHECK-NEXT: 2101f4: d2ffff84 mov x4, #-1125899906842624 +# CHECK-NEXT: 2101f8: f2e00084 movk x4, #4, lsl #48 +# CHECK-NEXT: 2101fc: f2ffff84 movk x4, #65532, lsl #48 diff --git a/lld/test/ELF/arm-bl-v6-inrange.s b/lld/test/ELF/arm-bl-v6-inrange.s index fe7cba5..24e10b5 100644 --- a/lld/test/ELF/arm-bl-v6-inrange.s +++ b/lld/test/ELF/arm-bl-v6-inrange.s @@ -29,14 +29,14 @@ thumbfunc: // CHECK: Disassembly of section .callee1: // CHECK-EMPTY: // CHECK-NEXT: <thumbfunc>: -// CHECK-NEXT: 100004: 70 47 bx lr +// CHECK-NEXT: 100004: 4770 bx lr // CHECK-EMPTY: // CHECK-NEXT: Disassembly of section .caller: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 500000: 00 f4 00 f8 bl 0x100004 <thumbfunc> -// CHECK-NEXT: 500004: ff f3 fe ef blx 0x900004 <armfunc> -// CHECK-NEXT: 500008: 70 47 bx lr +// CHECK-NEXT: 500000: f400 f800 bl 0x100004 <thumbfunc> +// CHECK-NEXT: 500004: f3ff effe blx 0x900004 <armfunc> +// CHECK-NEXT: 500008: 4770 bx lr .arm .section .callee_high, "ax", %progbits @@ -47,4 +47,4 @@ armfunc: // CHECK: Disassembly of section .callee2: // CHECK-EMPTY: // CHECK-NEXT: <armfunc>: -// CHECK-NEXT: 900004: 1e ff 2f e1 bx lr +// CHECK-NEXT: 900004: e12fff1e bx lr diff --git a/lld/test/ELF/arm-bl-v6.s b/lld/test/ELF/arm-bl-v6.s index 3d0c052..107c988 100644 --- a/lld/test/ELF/arm-bl-v6.s +++ b/lld/test/ELF/arm-bl-v6.s @@ -28,8 +28,8 @@ _start: // CHECK-ARM1: Disassembly of section .text: // CHECK-ARM1-EMPTY: // CHECK-ARM1-NEXT: <_start>: -// CHECK-ARM1-NEXT: 21000: 00 00 00 fa blx 0x21008 <thumbfunc> -// CHECK-ARM1-NEXT: 21004: 1e ff 2f e1 bx lr +// CHECK-ARM1-NEXT: 21000: fa000000 blx 0x21008 <thumbfunc> +// CHECK-ARM1-NEXT: 21004: e12fff1e bx lr .thumb .section .text.2, "ax", %progbits .globl thumbfunc @@ -38,14 +38,14 @@ thumbfunc: bl farthumbfunc // CHECK-THUMB1: <thumbfunc>: -// CHECK-THUMB1-NEXT: 21008: 00 f2 00 e8 blx 0x22100c <__ARMv5ABSLongThunk_farthumbfunc> +// CHECK-THUMB1-NEXT: 21008: f200 e800 blx 0x22100c <__ARMv5ABSLongThunk_farthumbfunc> /// 6 Megabytes, enough to make farthumbfunc out of range of caller /// on a v6 Arm, but not on a v7 Arm. .section .text.3, "ax", %progbits .space 0x200000 // CHECK-ARM2: <__ARMv5ABSLongThunk_farthumbfunc>: -// CHECK-ARM2-NEXT: 22100c: 04 f0 1f e5 ldr pc, [pc, #-4] +// CHECK-ARM2-NEXT: 22100c: e51ff004 ldr pc, [pc, #-4] // CHECK-ARM2: <$d>: // CHECK-ARM2-NEXT: 221010: 01 20 62 00 .word 0x00622001 .section .text.4, "ax", %progbits @@ -62,4 +62,4 @@ thumbfunc: farthumbfunc: bx lr // CHECK-THUMB2: <farthumbfunc>: -// CHECK-THUMB2-NEXT: 622000: 70 47 bx lr +// CHECK-THUMB2-NEXT: 622000: 4770 bx lr diff --git a/lld/test/ELF/arm-blx.s b/lld/test/ELF/arm-blx.s index 25e26911..73e1d87 100644 --- a/lld/test/ELF/arm-blx.s +++ b/lld/test/ELF/arm-blx.s @@ -75,44 +75,44 @@ callee_arm_high: // CHECK: Disassembly of section .callee1: // CHECK-EMPTY: // CHECK-NEXT: <callee_low>: -// CHECK-NEXT: b4: 70 47 bx lr +// CHECK-NEXT: b4: 4770 bx lr // CHECK: <callee_low2>: -// CHECK-NEXT: b6: 70 47 bx lr +// CHECK-NEXT: b6: 4770 bx lr // CHECK: Disassembly of section .callee2: // CHECK-EMPTY: // CHECK-NEXT: <callee_arm_low>: -// CHECK-NEXT: 100: 1e ff 2f e1 bx lr +// CHECK-NEXT: 100: e12fff1e bx lr // CHECK: Disassembly of section .caller: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 10000: 2b c0 ff fa blx 0xb4 <callee_low> -// CHECK-NEXT: 10004: 2a c0 ff fa blx 0xb4 <callee_low> -// CHECK-NEXT: 10008: 29 c0 ff fb blx 0xb6 <callee_low2> -// CHECK-NEXT: 1000c: 28 c0 ff fb blx 0xb6 <callee_low2> -// CHECK-NEXT: 10010: 3a 00 00 fa blx 0x10100 <callee_high> -// CHECK-NEXT: 10014: 39 00 00 fa blx 0x10100 <callee_high> -// CHECK-NEXT: 10018: 38 00 00 fb blx 0x10102 <callee_high2> -// CHECK-NEXT: 1001c: 37 00 00 fb blx 0x10102 <callee_high2> -/// 0x2010024 = blx_far -// CHECK-NEXT: 10020: ff ff 7f fa blx 0x2010024 -/// 0x2010028 = blx_far2 -// CHECK-NEXT: 10024: ff ff 7f fa blx 0x2010028 -// CHECK-NEXT: 10028: 34 c0 ff eb bl 0x100 <callee_arm_low> -// CHECK-NEXT: 1002c: 33 c0 ff eb bl 0x100 <callee_arm_low> -// CHECK-NEXT: 10030: 72 00 00 eb bl 0x10200 <callee_arm_high> -// CHECK-NEXT: 10034: 71 00 00 eb bl 0x10200 <callee_arm_high> -// CHECK-NEXT: 10038: 1e ff 2f e1 bx lr +// CHECK-NEXT: 10000: faffc02b blx 0xb4 <callee_low> +// CHECK-NEXT: 10004: faffc02a blx 0xb4 <callee_low> +// CHECK-NEXT: 10008: fbffc029 blx 0xb6 <callee_low2> +// CHECK-NEXT: 1000c: fbffc028 blx 0xb6 <callee_low2> +// CHECK-NEXT: 10010: fa00003a blx 0x10100 <callee_high> +// CHECK-NEXT: 10014: fa000039 blx 0x10100 <callee_high> +// CHECK-NEXT: 10018: fb000038 blx 0x10102 <callee_high2> +// CHECK-NEXT: 1001c: fb000037 blx 0x10102 <callee_high2> +/// 0x2010024 = blx_far +// CHECK-NEXT: 10020: fa7fffff blx 0x2010024 +/// 0x2010028 = blx_far2 +// CHECK-NEXT: 10024: fa7fffff blx 0x2010028 +// CHECK-NEXT: 10028: ebffc034 bl 0x100 <callee_arm_low> +// CHECK-NEXT: 1002c: ebffc033 bl 0x100 <callee_arm_low> +// CHECK-NEXT: 10030: eb000072 bl 0x10200 <callee_arm_high> +// CHECK-NEXT: 10034: eb000071 bl 0x10200 <callee_arm_high> +// CHECK-NEXT: 10038: e12fff1e bx lr // CHECK: Disassembly of section .callee3: // CHECK-EMPTY: // CHECK: <callee_high>: -// CHECK-NEXT: 10100: 70 47 bx lr +// CHECK-NEXT: 10100: 4770 bx lr // CHECK: <callee_high2>: -// CHECK-NEXT: 10102: 70 47 bx lr +// CHECK-NEXT: 10102: 4770 bx lr // CHECK: Disassembly of section .callee4: // CHECK-EMPTY: // CHECK-NEXT: <callee_arm_high>: -// CHECK-NEXT: 10200: 1e ff 2f e1 bx lr +// CHECK-NEXT: 10200: e12fff1e bx lr diff --git a/lld/test/ELF/arm-branch-undef-weak-plt-thunk.s b/lld/test/ELF/arm-branch-undef-weak-plt-thunk.s index f75fb6c..3ada2c3 100644 --- a/lld/test/ELF/arm-branch-undef-weak-plt-thunk.s +++ b/lld/test/ELF/arm-branch-undef-weak-plt-thunk.s @@ -24,13 +24,13 @@ _start: // CHECK: Disassembly of section .text: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 201e4: 00 00 00 ea b 0x201ec <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for> -// CHECK-NEXT: 201e8: 02 00 00 eb bl 0x201f8 <__ARMv7ABSLongThunk_bar2> +// CHECK-NEXT: 201e4: ea000000 b 0x201ec <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for> +// CHECK-NEXT: 201e8: eb000002 bl 0x201f8 <__ARMv7ABSLongThunk_bar2> // CHECK: <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for>: -// CHECK-NEXT: 201ec: 40 c2 00 e3 movw r12, #576 -// CHECK-NEXT: 201f0: 02 c2 40 e3 movt r12, #514 -// CHECK-NEXT: 201f4: 1c ff 2f e1 bx r12 +// CHECK-NEXT: 201ec: e300c240 movw r12, #576 +// CHECK-NEXT: 201f0: e340c202 movt r12, #514 +// CHECK-NEXT: 201f4: e12fff1c bx r12 // CHECK: <__ARMv7ABSLongThunk_bar2>: -// CHECK-NEXT: 201f8: 30 c2 00 e3 movw r12, #560 -// CHECK-NEXT: 201fc: 02 c2 40 e3 movt r12, #514 -// CHECK-NEXT: 20200: 1c ff 2f e1 bx r12 +// CHECK-NEXT: 201f8: e300c230 movw r12, #560 +// CHECK-NEXT: 201fc: e340c202 movt r12, #514 +// CHECK-NEXT: 20200: e12fff1c bx r12 diff --git a/lld/test/ELF/arm-exidx-order.s b/lld/test/ELF/arm-exidx-order.s index efff7b5..38adae2 100644 --- a/lld/test/ELF/arm-exidx-order.s +++ b/lld/test/ELF/arm-exidx-order.s @@ -134,32 +134,32 @@ f3: // CHECK-SCRIPT: Disassembly of section .text: // CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-NEXT: <func4>: -// CHECK-SCRIPT-NEXT: 11000: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 11000: e12fff1e bx lr // CHECK-SCRIPT: <func5>: -// CHECK-SCRIPT-NEXT: 11004: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 11004: e12fff1e bx lr // CHECK-SCRIPT: <_start>: -// CHECK-SCRIPT-NEXT: 11008: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 11008: e12fff1e bx lr // CHECK-SCRIPT: <f1>: -// CHECK-SCRIPT-NEXT: 1100c: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 1100c: e12fff1e bx lr // CHECK-SCRIPT: <f2>: -// CHECK-SCRIPT-NEXT: 11010: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 11010: e12fff1e bx lr // CHECK-SCRIPT: <f3>: -// CHECK-SCRIPT-NEXT: 11014: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 11014: e12fff1e bx lr // CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-NEXT: Disassembly of section .func1: // CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-NEXT: <func1>: -// CHECK-SCRIPT-NEXT: 11018: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 11018: e12fff1e bx lr // CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-NEXT: Disassembly of section .func2: // CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-NEXT: <func2>: -// CHECK-SCRIPT-NEXT: 1101c: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 1101c: e12fff1e bx lr // CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-NEXT: Disassembly of section .func3: // CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-NEXT: <func3>: -// CHECK-SCRIPT-NEXT: 11020: 1e ff 2f e1 bx lr +// CHECK-SCRIPT-NEXT: 11020: e12fff1e bx lr /// Check that the .ARM.exidx section is sorted in order as the functions /// The offset in field 1, is 32-bit so in the binary the most significant bit diff --git a/lld/test/ELF/arm-force-pi-thunk.s b/lld/test/ELF/arm-force-pi-thunk.s index 8cec1ab..9fc0896 100644 --- a/lld/test/ELF/arm-force-pi-thunk.s +++ b/lld/test/ELF/arm-force-pi-thunk.s @@ -33,24 +33,24 @@ low_target2: // CHECK: Disassembly of section .text_low: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 94: 70 47 bx lr +// CHECK-NEXT: 94: 4770 bx lr // CHECK: <low_target>: -// CHECK-NEXT: 96: 00 f0 03 f8 bl 0xa0 <__ThumbV7PILongThunk_high_target> -// CHECK-NEXT: 9a: 00 f0 07 f8 bl 0xac <__ThumbV7PILongThunk_high_target2> -// CHECK-NEXT: 9e: d4 d4 +// CHECK-NEXT: 96: f000 f803 bl 0xa0 <__ThumbV7PILongThunk_high_target> +// CHECK-NEXT: 9a: f000 f807 bl 0xac <__ThumbV7PILongThunk_high_target2> +// CHECK-NEXT: 9e: d4d4 // CHECK: <__ThumbV7PILongThunk_high_target>: -// CHECK-NEXT: a0: 4f f6 55 7c movw r12, #65365 -// CHECK-NEXT: a4: c0 f2 ff 1c movt r12, #511 -// CHECK-NEXT: a8: fc 44 add r12, pc -// CHECK-NEXT: aa: 60 47 bx r12 +// CHECK-NEXT: a0: f64f 7c55 movw r12, #65365 +// CHECK-NEXT: a4: f2c0 1cff movt r12, #511 +// CHECK-NEXT: a8: 44fc add r12, pc +// CHECK-NEXT: aa: 4760 bx r12 // CHECK: <__ThumbV7PILongThunk_high_target2>: -// CHECK-NEXT: ac: 4f f6 69 7c movw r12, #65385 -// CHECK-NEXT: b0: c0 f2 ff 1c movt r12, #511 -// CHECK-NEXT: b4: fc 44 add r12, pc -// CHECK-NEXT: b6: 60 47 bx r12 +// CHECK-NEXT: ac: f64f 7c69 movw r12, #65385 +// CHECK-NEXT: b0: f2c0 1cff movt r12, #511 +// CHECK-NEXT: b4: 44fc add r12, pc +// CHECK-NEXT: b6: 4760 bx r12 // CHECK: <low_target2>: -// CHECK-NEXT: b8: ff f7 f2 ff bl 0xa0 <__ThumbV7PILongThunk_high_target> -// CHECK-NEXT: bc: ff f7 f6 ff bl 0xac <__ThumbV7PILongThunk_high_target2> +// CHECK-NEXT: b8: f7ff fff2 bl 0xa0 <__ThumbV7PILongThunk_high_target> +// CHECK-NEXT: bc: f7ff fff6 bl 0xac <__ThumbV7PILongThunk_high_target2> .section .text_high, "ax", %progbits @@ -72,18 +72,18 @@ high_target2: // CHECK: Disassembly of section .text_high: // CHECK-EMPTY: // CHECK-NEXT: <high_target>: -// CHECK-NEXT: 2000000: 00 f0 02 f8 bl 0x2000008 <__ThumbV7PILongThunk_low_target> -// CHECK-NEXT: 2000004: 00 f0 06 f8 bl 0x2000014 <__ThumbV7PILongThunk_low_target2> +// CHECK-NEXT: 2000000: f000 f802 bl 0x2000008 <__ThumbV7PILongThunk_low_target> +// CHECK-NEXT: 2000004: f000 f806 bl 0x2000014 <__ThumbV7PILongThunk_low_target2> // CHECK: <__ThumbV7PILongThunk_low_target>: -// CHECK-NEXT: 2000008: 40 f2 83 0c movw r12, #131 -// CHECK-NEXT: 200000c: cf f6 00 6c movt r12, #65024 -// CHECK-NEXT: 2000010: fc 44 add r12, pc -// CHECK-NEXT: 2000012: 60 47 bx r12 +// CHECK-NEXT: 2000008: f240 0c83 movw r12, #131 +// CHECK-NEXT: 200000c: f6cf 6c00 movt r12, #65024 +// CHECK-NEXT: 2000010: 44fc add r12, pc +// CHECK-NEXT: 2000012: 4760 bx r12 // CHECK: <__ThumbV7PILongThunk_low_target2>: -// CHECK-NEXT: 2000014: 40 f2 99 0c movw r12, #153 -// CHECK-NEXT: 2000018: cf f6 00 6c movt r12, #65024 -// CHECK-NEXT: 200001c: fc 44 add r12, pc -// CHECK-NEXT: 200001e: 60 47 bx r12 +// CHECK-NEXT: 2000014: f240 0c99 movw r12, #153 +// CHECK-NEXT: 2000018: f6cf 6c00 movt r12, #65024 +// CHECK-NEXT: 200001c: 44fc add r12, pc +// CHECK-NEXT: 200001e: 4760 bx r12 // CHECK: <high_target2>: -// CHECK-NEXT: 2000020: ff f7 f2 ff bl 0x2000008 <__ThumbV7PILongThunk_low_target> -// CHECK-NEXT: 2000024: ff f7 f6 ff bl 0x2000014 <__ThumbV7PILongThunk_low_target2> +// CHECK-NEXT: 2000020: f7ff fff2 bl 0x2000008 <__ThumbV7PILongThunk_low_target> +// CHECK-NEXT: 2000024: f7ff fff6 bl 0x2000014 <__ThumbV7PILongThunk_low_target2> diff --git a/lld/test/ELF/arm-got-relative.s b/lld/test/ELF/arm-got-relative.s index 66996a6..9a7e52e 100644 --- a/lld/test/ELF/arm-got-relative.s +++ b/lld/test/ELF/arm-got-relative.s @@ -43,10 +43,10 @@ function: // CODE: Disassembly of section .text: // CODE-EMPTY: // CODE-NEXT: <_start>: -// CODE-NEXT: 101a0: 08 30 9f e5 ldr r3, [pc, #8] -// CODE-NEXT: 101a4: 08 20 9f e5 ldr r2, [pc, #8] -// CODE-NEXT: 101a8: 03 00 8f e0 add r0, pc, r3 -// CODE-NEXT: 101ac: 1e ff 2f e1 bx lr +// CODE-NEXT: 101a0: e59f3008 ldr r3, [pc, #8] +// CODE-NEXT: 101a4: e59f2008 ldr r2, [pc, #8] +// CODE-NEXT: 101a8: e08f0003 add r0, pc, r3 +// CODE-NEXT: 101ac: e12fff1e bx lr // CODE: <$d.1>: // (_GLOBAL_OFFSET_TABLE_ = 0x220c) - (0x11a8 + 8) = 0x105c // CODE-NEXT: 101b0: 5c 00 01 00 diff --git a/lld/test/ELF/arm-icf-exidx.s b/lld/test/ELF/arm-icf-exidx.s index 27ebad6..b4644c8 100644 --- a/lld/test/ELF/arm-icf-exidx.s +++ b/lld/test/ELF/arm-icf-exidx.s @@ -28,7 +28,7 @@ __aeabi_unwind_cpp_pr0: // CHECK: Disassembly of section .text: // CHECK-EMPTY: // CHECK-NEXT: <g>: -// CHECK-NEXT: 200ec: 1e ff 2f e1 bx lr +// CHECK-NEXT: 200ec: e12fff1e bx lr // CHECK: <__aeabi_unwind_cpp_pr0>: -// CHECK-NEXT: 200f0: 00 f0 20 e3 nop -// CHECK-NEXT: 200f4: 1e ff 2f e1 bx lr +// CHECK-NEXT: 200f0: e320f000 nop +// CHECK-NEXT: 200f4: e12fff1e bx lr diff --git a/lld/test/ELF/arm-long-thunk-converge.s b/lld/test/ELF/arm-long-thunk-converge.s index 19daeca..b7f8a30 100644 --- a/lld/test/ELF/arm-long-thunk-converge.s +++ b/lld/test/ELF/arm-long-thunk-converge.s @@ -6,22 +6,22 @@ // RUN: rm -f %t2 // CHECK1: <__ARMv7ABSLongThunk_bar>: -// CHECK1-NEXT: 0: 0c c0 00 e3 movw r12, #12 -// CHECK1-NEXT: 4: 00 c2 40 e3 movt r12, #512 -// CHECK1-NEXT: 8: 1c ff 2f e1 bx r12 +// CHECK1-NEXT: 0: e300c00c movw r12, #12 +// CHECK1-NEXT: 4: e340c200 movt r12, #512 +// CHECK1-NEXT: 8: e12fff1c bx r12 // CHECK1: <foo>: -// CHECK1-NEXT: c: fb ff ff eb bl 0x0 <__ARMv7ABSLongThunk_bar> +// CHECK1-NEXT: c: ebfffffb bl 0x0 <__ARMv7ABSLongThunk_bar> .section .foo,"ax",%progbits,unique,1 foo: bl bar // CHECK2: <__ARMv7ABSLongThunk_foo>: -// CHECK2-NEXT: 2000000: 0c c0 00 e3 movw r12, #12 -// CHECK2-NEXT: 2000004: 00 c0 40 e3 movt r12, #0 -// CHECK2-NEXT: 2000008: 1c ff 2f e1 bx r12 +// CHECK2-NEXT: 2000000: e300c00c movw r12, #12 +// CHECK2-NEXT: 2000004: e340c000 movt r12, #0 +// CHECK2-NEXT: 2000008: e12fff1c bx r12 // CHECK2: <bar>: -// CHECK2-NEXT: 200000c: fb ff ff eb bl 0x2000000 <__ARMv7ABSLongThunk_foo> +// CHECK2-NEXT: 200000c: ebfffffb bl 0x2000000 <__ARMv7ABSLongThunk_foo> .section .bar,"ax",%progbits,unique,1 bar: diff --git a/lld/test/ELF/arm-reloc-abs32.s b/lld/test/ELF/arm-reloc-abs32.s index 74676ca..a9f0642 100644 --- a/lld/test/ELF/arm-reloc-abs32.s +++ b/lld/test/ELF/arm-reloc-abs32.s @@ -13,10 +13,10 @@ _start: // S + A = 0x124 // CHECK: Disassembly of section .R_ARM_ABS32POS: // CHECK-EMPTY: -// CHECK: 24 01 00 00 +// CHECK: 00000124 .section .R_ARM_ABS32NEG, "ax",%progbits .word foo - 0x24 // S = 0x100, A = -0x24 // CHECK: Disassembly of section .R_ARM_ABS32NEG: // CHECK-EMPTY: -// CHECK: dc 00 00 00 +// CHECK: 000000dc diff --git a/lld/test/ELF/arm-sbrel32.s b/lld/test/ELF/arm-sbrel32.s index 4ebafad3..075dfeb 100644 --- a/lld/test/ELF/arm-sbrel32.s +++ b/lld/test/ELF/arm-sbrel32.s @@ -33,7 +33,7 @@ foo4: .space 4 // CHECK: Disassembly of section .text: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 200d4: 1e ff 2f e1 bx lr +// CHECK-NEXT: 200d4: e12fff1e bx lr // CHECK: 200d8: 00 00 00 00 .word 0x00000000 // CHECK-NEXT: 200dc: 04 00 00 00 .word 0x00000004 // CHECK-NEXT: 200e0: 08 00 00 00 .word 0x00000008 diff --git a/lld/test/ELF/arm-thumb-branch.s b/lld/test/ELF/arm-thumb-branch.s index 7e97b55..68b3681 100644 --- a/lld/test/ELF/arm-thumb-branch.s +++ b/lld/test/ELF/arm-thumb-branch.s @@ -42,26 +42,26 @@ callee_high: // CHECK: Disassembly of section .callee1: // CHECK-EMPTY: // CHECK-NEXT: <callee_low>: -// CHECK-NEXT: b4: 70 47 bx lr +// CHECK-NEXT: b4: 4770 bx lr // CHECK-EMPTY: // CHECK-NEXT: Disassembly of section .caller: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 10000: f0 f7 58 f8 bl 0xb4 <callee_low> -// CHECK-NEXT: 10004: f0 f7 56 b8 b.w 0xb4 <callee_low> -// CHECK-NEXT: 10008: 30 f4 54 a8 beq.w 0xb4 <callee_low> -// CHECK-NEXT: 1000c: 00 f0 0c f8 bl 0x10028 <callee_high> -// CHECK-NEXT: 10010: 00 f0 0a b8 b.w 0x10028 <callee_high> -// CHECK-NEXT: 10014: 40 f0 08 80 bne.w 0x10028 <callee_high> +// CHECK-NEXT: 10000: f7f0 f858 bl 0xb4 <callee_low> +// CHECK-NEXT: 10004: f7f0 b856 b.w 0xb4 <callee_low> +// CHECK-NEXT: 10008: f430 a854 beq.w 0xb4 <callee_low> +// CHECK-NEXT: 1000c: f000 f80c bl 0x10028 <callee_high> +// CHECK-NEXT: 10010: f000 b80a b.w 0x10028 <callee_high> +// CHECK-NEXT: 10014: f040 8008 bne.w 0x10028 <callee_high> /// far_uncond = 0x101001b -// CHECK-NEXT: 10018: ff f3 ff d7 bl 0x101001a -// CHECK-NEXT: 1001c: ff f3 fd 97 b.w 0x101001a +// CHECK-NEXT: 10018: f3ff d7ff bl 0x101001a +// CHECK-NEXT: 1001c: f3ff 97fd b.w 0x101001a /// far_cond = 0x110023 -// CHECK-NEXT: 10020: 3f f3 ff af bgt.w 0x110022 -// CHECK-NEXT: 10024: 70 47 bx lr +// CHECK-NEXT: 10020: f33f afff bgt.w 0x110022 +// CHECK-NEXT: 10024: 4770 bx lr // CHECK-NEXT: 10026: // CHECK-EMPTY: // CHECK-NEXT: Disassembly of section .callee2: // CHECK-EMPTY: // CHECK-NEXT: <callee_high>: -// CHECK-NEXT: 10028: 70 47 bx lr +// CHECK-NEXT: 10028: 4770 bx lr diff --git a/lld/test/ELF/arm-thumb-condbranch-thunk.s b/lld/test/ELF/arm-thumb-condbranch-thunk.s index 2f56de7..211b05a 100644 --- a/lld/test/ELF/arm-thumb-condbranch-thunk.s +++ b/lld/test/ELF/arm-thumb-condbranch-thunk.s @@ -36,12 +36,12 @@ _start: // CHECK1: Disassembly of section .text: // CHECK1-EMPTY: // CHECK1-NEXT: <tfunc00>: -// CHECK1-NEXT: 80000: 70 47 bx lr -// CHECK1-NEXT: 80002: 7f f3 ff d7 bl 0x1000004 <__Thumbv7ABSLongThunk_tfunc33> +// CHECK1-NEXT: 80000: 4770 bx lr +// CHECK1-NEXT: 80002: f37f d7ff bl 0x1000004 <__Thumbv7ABSLongThunk_tfunc33> // CHECK1: <__Thumbv7ABSLongThunk_tfunc05>: -// CHECK1-NEXT: 80008: 7f f2 fa bf b.w 0x300000 <tfunc05> +// CHECK1-NEXT: 80008: f27f bffa b.w 0x300000 <tfunc05> // CHECK1: <__Thumbv7ABSLongThunk_tfunc00>: -// CHECK1-NEXT: 8000c: ff f7 f8 bf b.w 0x80000 <tfunc00> +// CHECK1-NEXT: 8000c: f7ff bff8 b.w 0x80000 <tfunc00> FUNCTION 01 // tfunc02 is within range of tfunc02 beq.w tfunc02 @@ -49,16 +49,16 @@ _start: // create a new one. bne.w tfunc05 // CHECK2: <tfunc01>: -// CHECK2-NEXT: 100000: 70 47 bx lr -// CHECK2-NEXT: 100002: 3f f0 fd a7 beq.w 0x180000 <tfunc02> -// CHECK2-NEXT: 100006: 7f f4 ff a7 bne.w 0x80008 <__Thumbv7ABSLongThunk_tfunc05> +// CHECK2-NEXT: 100000: 4770 bx lr +// CHECK2-NEXT: 100002: f03f a7fd beq.w 0x180000 <tfunc02> +// CHECK2-NEXT: 100006: f47f a7ff bne.w 0x80008 <__Thumbv7ABSLongThunk_tfunc05> FUNCTION 02 // We can reach the Thunk Section created for bne.w tfunc05 bne.w tfunc05 beq.w tfunc00 -// CHECK3: 180000: 70 47 bx lr -// CHECK3-NEXT: 180002: 40 f4 01 80 bne.w 0x80008 <__Thumbv7ABSLongThunk_tfunc05> -// CHECK3-NEXT: 180006: 00 f4 01 80 beq.w 0x8000c <__Thumbv7ABSLongThunk_tfunc00> +// CHECK3: 180000: 4770 bx lr +// CHECK3-NEXT: 180002: f440 8001 bne.w 0x80008 <__Thumbv7ABSLongThunk_tfunc05> +// CHECK3-NEXT: 180006: f400 8001 beq.w 0x8000c <__Thumbv7ABSLongThunk_tfunc00> FUNCTION 03 FUNCTION 04 FUNCTION 05 @@ -67,13 +67,13 @@ _start: FUNCTION 08 FUNCTION 09 // CHECK4: <__Thumbv7ABSLongThunk_tfunc03>: -// CHECK4-NEXT: 500004: ff f4 fc bf b.w 0x200000 <tfunc03> +// CHECK4-NEXT: 500004: f4ff bffc b.w 0x200000 <tfunc03> FUNCTION 10 // We can't reach any Thunk Section, create a new one beq.w tfunc03 // CHECK5: <tfunc10>: -// CHECK5-NEXT: 580000: 70 47 bx lr -// CHECK5-NEXT: 580002: 3f f4 ff a7 beq.w 0x500004 <__Thumbv7ABSLongThunk_tfunc03> +// CHECK5-NEXT: 580000: 4770 bx lr +// CHECK5-NEXT: 580002: f43f a7ff beq.w 0x500004 <__Thumbv7ABSLongThunk_tfunc03> FUNCTION 11 FUNCTION 12 FUNCTION 13 @@ -96,13 +96,13 @@ _start: FUNCTION 30 FUNCTION 31 // CHECK6: <__Thumbv7ABSLongThunk_tfunc33>: -// CHECK6-NEXT: 1000004: ff f0 fc bf b.w 0x1100000 <tfunc33> +// CHECK6-NEXT: 1000004: f0ff bffc b.w 0x1100000 <tfunc33> // CHECK6: <__Thumbv7ABSLongThunk_tfunc00>: -// CHECK6-NEXT: 1000008: 7f f4 fa 97 b.w 0x80000 <tfunc00> +// CHECK6-NEXT: 1000008: f47f 97fa b.w 0x80000 <tfunc00> FUNCTION 32 FUNCTION 33 // We should be able to reach an existing ThunkSection. b.w tfunc00 // CHECK7: <tfunc33>: -// CHECK7-NEXT: 1100000: 70 47 bx lr -// CHECK7-NEXT: 1100002: 00 f7 01 b8 b.w 0x1000008 <__Thumbv7ABSLongThunk_tfunc00> +// CHECK7-NEXT: 1100000: 4770 bx lr +// CHECK7-NEXT: 1100002: f700 b801 b.w 0x1000008 <__Thumbv7ABSLongThunk_tfunc00> diff --git a/lld/test/ELF/arm-thumb-interwork-thunk-v5.s b/lld/test/ELF/arm-thumb-interwork-thunk-v5.s index 8144ad5..1872977 100644 --- a/lld/test/ELF/arm-thumb-interwork-thunk-v5.s +++ b/lld/test/ELF/arm-thumb-interwork-thunk-v5.s @@ -27,32 +27,32 @@ _start: bx lr // CHECK: <_start>: -// CHECK-NEXT: 21000: 03 00 00 ea b 0x21014 <__ARMv5ABSLongThunk_thumb_func> -// CHECK-NEXT: 21004: 01 00 00 fa blx 0x21010 <thumb_func> -// CHECK-NEXT: 21008: 00 00 00 fa blx 0x21010 <thumb_func> -// CHECK-NEXT: 2100c: 1e ff 2f e1 bx lr +// CHECK-NEXT: 21000: ea000003 b 0x21014 <__ARMv5ABSLongThunk_thumb_func> +// CHECK-NEXT: 21004: fa000001 blx 0x21010 <thumb_func> +// CHECK-NEXT: 21008: fa000000 blx 0x21010 <thumb_func> +// CHECK-NEXT: 2100c: e12fff1e bx lr // CHECK: <thumb_func>: -// CHECK-NEXT: 21010: 70 47 bx lr +// CHECK-NEXT: 21010: 4770 bx lr // CHECK: <__ARMv5ABSLongThunk_thumb_func>: -// CHECK-NEXT: 21014: 04 f0 1f e5 ldr pc, [pc, #-4] +// CHECK-NEXT: 21014: e51ff004 ldr pc, [pc, #-4] // CHECK: <$d>: // CHECK-NEXT: 21018: 11 10 02 00 .word 0x00021011 // CHECK-PI: <_start>: -// CHECK-PI-NEXT: 11000: 03 00 00 ea b 0x11014 <__ARMV5PILongThunk_thumb_func> -// CHECK-PI-NEXT: 11004: 01 00 00 fa blx 0x11010 <thumb_func> -// CHECK-PI-NEXT: 11008: 00 00 00 fa blx 0x11010 <thumb_func> -// CHECK-PI-NEXT: 1100c: 1e ff 2f e1 bx lr +// CHECK-PI-NEXT: 11000: ea000003 b 0x11014 <__ARMV5PILongThunk_thumb_func> +// CHECK-PI-NEXT: 11004: fa000001 blx 0x11010 <thumb_func> +// CHECK-PI-NEXT: 11008: fa000000 blx 0x11010 <thumb_func> +// CHECK-PI-NEXT: 1100c: e12fff1e bx lr // CHECK-PI: <thumb_func>: -// CHECK-PI-NEXT: 11010: 70 47 bx lr +// CHECK-PI-NEXT: 11010: 4770 bx lr // CHECK-PI: <__ARMV5PILongThunk_thumb_func>: -// CHECK-PI-NEXT: 11014: 04 c0 9f e5 ldr r12, [pc, #4] -// CHECK-PI-NEXT: 11018: 0c c0 8f e0 add r12, pc, r12 -// CHECK-PI-NEXT: 1101c: 1c ff 2f e1 bx r12 +// CHECK-PI-NEXT: 11014: e59fc004 ldr r12, [pc, #4] +// CHECK-PI-NEXT: 11018: e08fc00c add r12, pc, r12 +// CHECK-PI-NEXT: 1101c: e12fff1c bx r12 // CHECK-PI: <$d>: // CHECK-PI-NEXT: 11020: f1 ff ff ff .word 0xfffffff1 diff --git a/lld/test/ELF/arm-thumb-mix-range-thunk-os.s b/lld/test/ELF/arm-thumb-mix-range-thunk-os.s index ad44b1e..9926ad6 100644 --- a/lld/test/ELF/arm-thumb-mix-range-thunk-os.s +++ b/lld/test/ELF/arm-thumb-mix-range-thunk-os.s @@ -61,22 +61,22 @@ _start: b afunc32 bne afunc32 // CHECK1: <afunc00>: -// CHECK1-NEXT: 100000: 1e ff 2f e1 bx lr -// CHECK1-NEXT: 100004: fd ff 7b fa blx 0x2000000 <tfunc31> -// CHECK1-NEXT: 100008: fd ff 3b ea b 0x1000004 <__ARMv7ABSLongThunk_tfunc31> -// CHECK1-NEXT: 10000c: fc ff 3b 0a beq 0x1000004 <__ARMv7ABSLongThunk_tfunc31> -// CHECK1-NEXT: 100010: fa ff 7f eb bl 0x2100000 <afunc32> -// CHECK1-NEXT: 100014: f9 ff 7f ea b 0x2100000 <afunc32> -// CHECK1-NEXT: 100018: f8 ff 7f 1a bne 0x2100000 <afunc32> +// CHECK1-NEXT: 100000: e12fff1e bx lr +// CHECK1-NEXT: 100004: fa7bfffd blx 0x2000000 <tfunc31> +// CHECK1-NEXT: 100008: ea3bfffd b 0x1000004 <__ARMv7ABSLongThunk_tfunc31> +// CHECK1-NEXT: 10000c: 0a3bfffc beq 0x1000004 <__ARMv7ABSLongThunk_tfunc31> +// CHECK1-NEXT: 100010: eb7ffffa bl 0x2100000 <afunc32> +// CHECK1-NEXT: 100014: ea7ffff9 b 0x2100000 <afunc32> +// CHECK1-NEXT: 100018: 1a7ffff8 bne 0x2100000 <afunc32> THUMBFUNCTION 01 // Expect Thumb bl to be in range (can use blx to change state) bl afunc14 // In range but need thunk to change state to Thumb b.w afunc14 // CHECK2: <tfunc01>: -// CHECK2-NEXT: 200000: 70 47 bx lr -// CHECK2-NEXT: 200002: ff f0 fe c7 blx 0xf00000 <afunc14> -// CHECK2-NEXT: 200006: 00 f2 03 90 b.w 0x1000010 <__Thumbv7ABSLongThunk_afunc14> +// CHECK2-NEXT: 200000: 4770 bx lr +// CHECK2-NEXT: 200002: f0ff c7fe blx 0xf00000 <afunc14> +// CHECK2-NEXT: 200006: f200 9003 b.w 0x1000010 <__Thumbv7ABSLongThunk_afunc14> ARMFUNCTION 02 THUMBFUNCTION 03 @@ -92,13 +92,13 @@ _start: THUMBFUNCTION 13 ARMFUNCTION 14 // CHECK3: <__ARMv7ABSLongThunk_tfunc31>: -// CHECK3-NEXT: 1000004: 01 c0 00 e3 movw r12, #1 -// CHECK3-NEXT: 1000008: 00 c2 40 e3 movt r12, #512 -// CHECK3-NEXT: 100000c: 1c ff 2f e1 bx r12 +// CHECK3-NEXT: 1000004: e300c001 movw r12, #1 +// CHECK3-NEXT: 1000008: e340c200 movt r12, #512 +// CHECK3-NEXT: 100000c: e12fff1c bx r12 // CHECK4: <__Thumbv7ABSLongThunk_afunc14>: -// CHECK4-NEXT: 1000010: 40 f2 00 0c movw r12, #0 -// CHECK4-NEXT: 1000014: c0 f2 f0 0c movt r12, #240 -// CHECK4-NEXT: 1000018: 60 47 bx r12 +// CHECK4-NEXT: 1000010: f240 0c00 movw r12, #0 +// CHECK4-NEXT: 1000014: f2c0 0cf0 movt r12, #240 +// CHECK4-NEXT: 1000018: 4760 bx r12 THUMBFUNCTION 15 ARMFUNCTION 16 THUMBFUNCTION 17 @@ -117,22 +117,22 @@ _start: ARMFUNCTION 30 // Expect precreated Thunk Section here // CHECK5: <__Thumbv7ABSLongThunk_afunc00>: -// CHECK5-NEXT: 1f00004: 40 f2 00 0c movw r12, #0 -// CHECK5-NEXT: 1f00008: c0 f2 10 0c movt r12, #16 -// CHECK5-NEXT: 1f0000c: 60 47 bx r12 +// CHECK5-NEXT: 1f00004: f240 0c00 movw r12, #0 +// CHECK5-NEXT: 1f00008: f2c0 0c10 movt r12, #16 +// CHECK5-NEXT: 1f0000c: 4760 bx r12 THUMBFUNCTION 31 ARMFUNCTION 32 THUMBFUNCTION 33 // Out of range, can only reach closest Thunk Section bl afunc00 // CHECK6: <tfunc33>: -// CHECK6-NEXT: 2200000: 70 47 bx lr -// CHECK6-NEXT: 2200002: ff f4 ff ff bl 0x1f00004 <__Thumbv7ABSLongThunk_afunc00> +// CHECK6-NEXT: 2200000: 4770 bx lr +// CHECK6-NEXT: 2200002: f4ff ffff bl 0x1f00004 <__Thumbv7ABSLongThunk_afunc00> ARMFUNCTION 34 // Out of range, can reach earlier Thunk Section // CHECK7: <afunc34>: -// CHECK7-NEXT: 2300000: 1e ff 2f e1 bx lr -// CHECK7-NEXT: 2300004: fe ff ef fa blx 0x1f00004 <__Thumbv7ABSLongThunk_afunc00> +// CHECK7-NEXT: 2300000: e12fff1e bx lr +// CHECK7-NEXT: 2300004: faeffffe blx 0x1f00004 <__Thumbv7ABSLongThunk_afunc00> bl afunc00 THUMBFUNCTION 35 ARMFUNCTION 36 @@ -147,9 +147,9 @@ _start: THUMBFUNCTION 45 // Expect precreated Thunk Section here // CHECK8: <__ARMv7ABSLongThunk_tfunc35>: -// CHECK8-NEXT: 2e00004: 01 c0 00 e3 movw r12, #1 -// CHECK8-NEXT: 2e00008: 40 c2 40 e3 movt r12, #576 -// CHECK8-NEXT: 2e0000c: 1c ff 2f e1 bx r12 +// CHECK8-NEXT: 2e00004: e300c001 movw r12, #1 +// CHECK8-NEXT: 2e00008: e340c240 movt r12, #576 +// CHECK8-NEXT: 2e0000c: e12fff1c bx r12 ARMFUNCTION 46 THUMBFUNCTION 47 ARMFUNCTION 48 @@ -157,11 +157,11 @@ _start: ARMFUNCTION 50 // Expect precreated Thunk Section here // CHECK9: <__Thumbv7ABSLongThunk_afunc34>: -// CHECK9-NEXT: 3300004: 40 f2 00 0c movw r12, #0 -// CHECK9-NEXT: 3300008: c0 f2 30 2c movt r12, #560 -// CHECK9-NEXT: 330000c: 60 47 bx r12 +// CHECK9-NEXT: 3300004: f240 0c00 movw r12, #0 +// CHECK9-NEXT: 3300008: f2c0 2c30 movt r12, #560 +// CHECK9-NEXT: 330000c: 4760 bx r12 // CHECK9: <__Thumbv7ABSLongThunk_tfunc35>: -// CHECK9-NEXT: 330000e: ff f4 f7 97 b.w 0x2400000 <tfunc35> +// CHECK9-NEXT: 330000e: f4ff 97f7 b.w 0x2400000 <tfunc35> THUMBFUNCTION 51 ARMFUNCTION 52 THUMBFUNCTION 53 @@ -180,14 +180,14 @@ _start: bl afunc34 b tfunc35 // CHECK10: <afunc64>: -// CHECK10-NEXT: 4100000: 1e ff 2f e1 bx lr -// CHECK10-NEXT: 4100004: fd ff 87 eb bl 0x2300000 <afunc34> -// CHECK10-NEXT: 4100008: fd ff b3 ea b 0x2e00004 <__ARMv7ABSLongThunk_tfunc35> +// CHECK10-NEXT: 4100000: e12fff1e bx lr +// CHECK10-NEXT: 4100004: eb87fffd bl 0x2300000 <afunc34> +// CHECK10-NEXT: 4100008: eab3fffd b 0x2e00004 <__ARMv7ABSLongThunk_tfunc35> THUMBFUNCTION 65 // afunc34 and tfunc35 are both out of range bl afunc34 bl tfunc35 // CHECK11: <tfunc65>: -// CHECK11: 4200000: 70 47 bx lr -// CHECK11-NEXT: 4200002: ff f4 ff d7 bl 0x3300004 <__Thumbv7ABSLongThunk_afunc34> -// CHECK11-NEXT: 4200006: 00 f5 02 d0 bl 0x330000e <__Thumbv7ABSLongThunk_tfunc35> +// CHECK11: 4200000: 4770 bx lr +// CHECK11-NEXT: 4200002: f4ff d7ff bl 0x3300004 <__Thumbv7ABSLongThunk_afunc34> +// CHECK11-NEXT: 4200006: f500 d002 bl 0x330000e <__Thumbv7ABSLongThunk_tfunc35> diff --git a/lld/test/ELF/arm-thumb-narrow-branch-check.s b/lld/test/ELF/arm-thumb-narrow-branch-check.s index cd782c4..394c7a0 100644 --- a/lld/test/ELF/arm-thumb-narrow-branch-check.s +++ b/lld/test/ELF/arm-thumb-narrow-branch-check.s @@ -62,33 +62,33 @@ callee_high_far = 0x180d // CHECK: Disassembly of section .callee_low: // CHECK-EMPTY: // CHECK-NEXT: <callee_low>: -// CHECK-NEXT: 1000: 70 47 bx lr +// CHECK-NEXT: 1000: 4770 bx lr // CHECK-EMPTY: // CHECK-NEXT: Disassembly of section .caller: // CHECK-EMPTY: // CHECK-NEXT: <callers>: /// callee_low_far = 0x809 -// CHECK-NEXT: 1004: 00 e4 b 0x808 -// CHECK-NEXT: 1006: fb e7 b 0x1000 <callee_low> -// CHECK-NEXT: 1008: 06 e0 b 0x1018 <callee_high> +// CHECK-NEXT: 1004: e400 b 0x808 +// CHECK-NEXT: 1006: e7fb b 0x1000 <callee_low> +// CHECK-NEXT: 1008: e006 b 0x1018 <callee_high> /// callee_high_far = 0x180d -// CHECK-NEXT: 100a: ff e3 b 0x180c +// CHECK-NEXT: 100a: e3ff b 0x180c /// callee_low_near = 0xfff -// CHECK-NEXT: 100c: f7 d0 beq 0xffe -// CHECK-NEXT: 100e: f7 d0 beq 0x1000 <callee_low> -// CHECK-NEXT: 1010: 02 d0 beq 0x1018 <callee_high> +// CHECK-NEXT: 100c: d0f7 beq 0xffe +// CHECK-NEXT: 100e: d0f7 beq 0x1000 <callee_low> +// CHECK-NEXT: 1010: d002 beq 0x1018 <callee_high> /// callee_high_near = 0x10ff -// CHECK-NEXT: 1012: 74 d0 beq 0x10fe -// CHECK-NEXT: 1014: 70 47 bx lr -// CHECK-NEXT: 1016: c0 46 mov r8, r8 +// CHECK-NEXT: 1012: d074 beq 0x10fe +// CHECK-NEXT: 1014: 4770 bx lr +// CHECK-NEXT: 1016: 46c0 mov r8, r8 // CHECK-EMPTY: // CHECK-NEXT: Disassembly of section .callee_high: // CHECK-EMPTY: // CHECK-NEXT: <callee_high>: -// CHECK-NEXT: 1018: 70 47 bx lr +// CHECK-NEXT: 1018: 4770 bx lr // CHECK-EMPTY: // CHECK-NEXT: Disassembly of section .text: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 101c: ff f7 f2 ff bl 0x1004 <callers> -// CHECK-NEXT: 1020: 70 47 bx lr +// CHECK-NEXT: 101c: f7ff fff2 bl 0x1004 <callers> +// CHECK-NEXT: 1020: 4770 bx lr diff --git a/lld/test/ELF/arm-thumb-plt-range-thunk-os.s b/lld/test/ELF/arm-thumb-plt-range-thunk-os.s index f5064c3..a6facd9 100644 --- a/lld/test/ELF/arm-thumb-plt-range-thunk-os.s +++ b/lld/test/ELF/arm-thumb-plt-range-thunk-os.s @@ -38,38 +38,38 @@ preemptible: // CHECK1: Disassembly of section .text: // CHECK1-EMPTY: // CHECK1-NEXT: <sym1>: -// CHECK1-NEXT: 2000000: 00 f0 00 d8 bl 0x2800004 <__ThumbV7PILongThunk_elsewhere> -// CHECK1-NEXT: 2000004: 00 f0 04 d8 bl 0x2800010 <__ThumbV7PILongThunk_preemptible> -// CHECK1-NEXT: 2000008: 70 47 bx lr +// CHECK1-NEXT: 2000000: f000 d800 bl 0x2800004 <__ThumbV7PILongThunk_elsewhere> +// CHECK1-NEXT: 2000004: f000 d804 bl 0x2800010 <__ThumbV7PILongThunk_preemptible> +// CHECK1-NEXT: 2000008: 4770 bx lr // CHECK1: <preemptible>: -// CHECK1-NEXT: 200000a: 00 f0 07 d8 bl 0x280001c <__ThumbV7PILongThunk_far_preemptible> -// CHECK1-NEXT: 200000e: 00 f0 0b d8 bl 0x2800028 <__ThumbV7PILongThunk_far_nonpreemptible> -// CHECK1-NEXT: 2000012: 00 f0 09 d8 bl 0x2800028 <__ThumbV7PILongThunk_far_nonpreemptible> -// CHECK1-NEXT: 2000016: 70 47 bx lr +// CHECK1-NEXT: 200000a: f000 d807 bl 0x280001c <__ThumbV7PILongThunk_far_preemptible> +// CHECK1-NEXT: 200000e: f000 d80b bl 0x2800028 <__ThumbV7PILongThunk_far_nonpreemptible> +// CHECK1-NEXT: 2000012: f000 d809 bl 0x2800028 <__ThumbV7PILongThunk_far_nonpreemptible> +// CHECK1-NEXT: 2000016: 4770 bx lr .section .text.2, "ax", %progbits .balign 0x0800000 bx lr // CHECK2: <__ThumbV7PILongThunk_elsewhere>: -// CHECK2-NEXT: 2800004: 40 f2 20 0c movw r12, #32 -// CHECK2-NEXT: 2800008: c0 f2 80 1c movt r12, #384 -// CHECK2-NEXT: 280000c: fc 44 add r12, pc -// CHECK2-NEXT: 280000e: 60 47 bx r12 +// CHECK2-NEXT: 2800004: f240 0c20 movw r12, #32 +// CHECK2-NEXT: 2800008: f2c0 1c80 movt r12, #384 +// CHECK2-NEXT: 280000c: 44fc add r12, pc +// CHECK2-NEXT: 280000e: 4760 bx r12 // CHECK2: <__ThumbV7PILongThunk_preemptible>: -// CHECK2-NEXT: 2800010: 40 f2 24 0c movw r12, #36 -// CHECK2-NEXT: 2800014: c0 f2 80 1c movt r12, #384 -// CHECK2-NEXT: 2800018: fc 44 add r12, pc -// CHECK2-NEXT: 280001a: 60 47 bx r12 +// CHECK2-NEXT: 2800010: f240 0c24 movw r12, #36 +// CHECK2-NEXT: 2800014: f2c0 1c80 movt r12, #384 +// CHECK2-NEXT: 2800018: 44fc add r12, pc +// CHECK2-NEXT: 280001a: 4760 bx r12 // CHECK2: <__ThumbV7PILongThunk_far_preemptible>: -// CHECK2-NEXT: 280001c: 40 f2 28 0c movw r12, #40 -// CHECK2-NEXT: 2800020: c0 f2 80 1c movt r12, #384 -// CHECK2-NEXT: 2800024: fc 44 add r12, pc -// CHECK2-NEXT: 2800026: 60 47 bx r12 +// CHECK2-NEXT: 280001c: f240 0c28 movw r12, #40 +// CHECK2-NEXT: 2800020: f2c0 1c80 movt r12, #384 +// CHECK2-NEXT: 2800024: 44fc add r12, pc +// CHECK2-NEXT: 2800026: 4760 bx r12 // CHECK2: <__ThumbV7PILongThunk_far_nonpreemptible>: -// CHECK2-NEXT: 2800028: 4f f6 cd 7c movw r12, #65485 -// CHECK2-NEXT: 280002c: c0 f2 7f 1c movt r12, #383 -// CHECK2-NEXT: 2800030: fc 44 add r12, pc -// CHECK2-NEXT: 2800032: 60 47 bx r12 +// CHECK2-NEXT: 2800028: f64f 7ccd movw r12, #65485 +// CHECK2-NEXT: 280002c: f2c0 1c7f movt r12, #383 +// CHECK2-NEXT: 2800030: 44fc add r12, pc +// CHECK2-NEXT: 2800032: 4760 bx r12 .section .text.3, "ax", %progbits .balign 0x2000000 @@ -83,35 +83,35 @@ far_nonpreemptible_alias: bl elsewhere // CHECK3: <far_preemptible>: -// CHECK3: 4000000: 00 f0 16 e8 blx 0x4000030 +// CHECK3: 4000000: f000 e816 blx 0x4000030 // CHECK4: Disassembly of section .plt: // CHECK4-EMPTY: // CHECK4-NEXT: <$a>: -// CHECK4-NEXT: 4000010: 04 e0 2d e5 str lr, [sp, #-4]! -// CHECK4-NEXT: 4000014: 00 e6 8f e2 add lr, pc, #0, #12 -// CHECK4-NEXT: 4000018: 20 ea 8e e2 add lr, lr, #32 -// CHECK4-NEXT: 400001c: a4 f0 be e5 ldr pc, [lr, #164]! +// CHECK4-NEXT: 4000010: e52de004 str lr, [sp, #-4]! +// CHECK4-NEXT: 4000014: e28fe600 add lr, pc, #0, #12 +// CHECK4-NEXT: 4000018: e28eea20 add lr, lr, #32 +// CHECK4-NEXT: 400001c: e5bef0a4 ldr pc, [lr, #164]! // CHECK4: <$d>: // CHECK4-NEXT: 4000020: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 4000024: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 4000028: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 400002c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4: <$a>: -// CHECK4-NEXT: 4000030: 00 c6 8f e2 add r12, pc, #0, #12 -// CHECK4-NEXT: 4000034: 20 ca 8c e2 add r12, r12, #32 -// CHECK4-NEXT: 4000038: 8c f0 bc e5 ldr pc, [r12, #140]! +// CHECK4-NEXT: 4000030: e28fc600 add r12, pc, #0, #12 +// CHECK4-NEXT: 4000034: e28cca20 add r12, r12, #32 +// CHECK4-NEXT: 4000038: e5bcf08c ldr pc, [r12, #140]! // CHECK4: <$d>: // CHECK4-NEXT: 400003c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4: <$a>: -// CHECK4-NEXT: 4000040: 00 c6 8f e2 add r12, pc, #0, #12 -// CHECK4-NEXT: 4000044: 20 ca 8c e2 add r12, r12, #32 -// CHECK4-NEXT: 4000048: 80 f0 bc e5 ldr pc, [r12, #128]! +// CHECK4-NEXT: 4000040: e28fc600 add r12, pc, #0, #12 +// CHECK4-NEXT: 4000044: e28cca20 add r12, r12, #32 +// CHECK4-NEXT: 4000048: e5bcf080 ldr pc, [r12, #128]! // CHECK4: <$d>: // CHECK4-NEXT: 400004c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4: <$a>: -// CHECK4-NEXT: 4000050: 00 c6 8f e2 add r12, pc, #0, #12 -// CHECK4-NEXT: 4000054: 20 ca 8c e2 add r12, r12, #32 -// CHECK4-NEXT: 4000058: 74 f0 bc e5 ldr pc, [r12, #116]! +// CHECK4-NEXT: 4000050: e28fc600 add r12, pc, #0, #12 +// CHECK4-NEXT: 4000054: e28cca20 add r12, r12, #32 +// CHECK4-NEXT: 4000058: e5bcf074 ldr pc, [r12, #116]! // CHECK4: <$d>: // CHECK4-NEXT: 400005c: d4 d4 d4 d4 .word 0xd4d4d4d4 diff --git a/lld/test/ELF/arm-thumb-plt-reloc.s b/lld/test/ELF/arm-thumb-plt-reloc.s index 22e4282..e1b6df6 100644 --- a/lld/test/ELF/arm-thumb-plt-reloc.s +++ b/lld/test/ELF/arm-thumb-plt-reloc.s @@ -25,16 +25,16 @@ _start: // CHECK: Disassembly of section .text: // CHECK-EMPTY: // CHECK-NEXT: <func1>: -// CHECK-NEXT: 200b4: 70 47 bx lr +// CHECK-NEXT: 200b4: 4770 bx lr // CHECK: <func2>: -// CHECK-NEXT: 200b6: 70 47 bx lr +// CHECK-NEXT: 200b6: 4770 bx lr // CHECK: <func3>: -// CHECK-NEXT: 200b8: 70 47 bx lr -// CHECK-NEXT: 200ba: d4 d4 +// CHECK-NEXT: 200b8: 4770 bx lr +// CHECK-NEXT: 200ba: d4d4 // CHECK: <_start>: -// CHECK-NEXT: 200bc: ff f7 fa ff bl 0x200b4 <func1> -// CHECK-NEXT: 200c0: ff f7 f9 ff bl 0x200b6 <func2> -// CHECK-NEXT: 200c4: ff f7 f8 ff bl 0x200b8 <func3> +// CHECK-NEXT: 200bc: f7ff fffa bl 0x200b4 <func1> +// CHECK-NEXT: 200c0: f7ff fff9 bl 0x200b6 <func2> +// CHECK-NEXT: 200c4: f7ff fff8 bl 0x200b8 <func3> // Expect PLT entries as symbols can be preempted // .text is Thumb and .plt is ARM, llvm-objdump can currently only disassemble @@ -42,27 +42,27 @@ _start: // DSO: Disassembly of section .text: // DSO-EMPTY: // DSO-NEXT: <func1>: -// DSO-NEXT: 10214: 70 47 bx lr +// DSO-NEXT: 10214: 4770 bx lr // DSO: <func2>: -// DSO-NEXT: 10216: 70 47 bx lr +// DSO-NEXT: 10216: 4770 bx lr // DSO: <func3>: -// DSO-NEXT: 10218: 70 47 bx lr -// DSO-NEXT: 1021a: d4 d4 +// DSO-NEXT: 10218: 4770 bx lr +// DSO-NEXT: 1021a: d4d4 // DSO: <_start>: // 0x10250 = PLT func1 -// DSO-NEXT: 1021c: 00 f0 18 e8 blx 0x10250 +// DSO-NEXT: 1021c: f000 e818 blx 0x10250 // 0x10260 = PLT func2 -// DSO-NEXT: 10220: 00 f0 1e e8 blx 0x10260 +// DSO-NEXT: 10220: f000 e81e blx 0x10260 // 0x10270 = PLT func3 -// DSO-NEXT: 10224: 00 f0 24 e8 blx 0x10270 +// DSO-NEXT: 10224: f000 e824 blx 0x10270 // DSO: Disassembly of section .plt: // DSO-EMPTY: // DSO-NEXT: <$a>: -// DSO-NEXT: 10230: 04 e0 2d e5 str lr, [sp, #-4]! +// DSO-NEXT: 10230: e52de004 str lr, [sp, #-4]! // (0x10234 + 8) + (0 RoR 12) + (32 RoR 20 = 0x20000) + 164 = 0x302e0 = .got.plt[2] -// DSO-NEXT: 10234: 00 e6 8f e2 add lr, pc, #0, #12 -// DSO-NEXT: 10238: 20 ea 8e e2 add lr, lr, #32, #20 -// DSO-NEXT: 1023c: a4 f0 be e5 ldr pc, [lr, #164]! +// DSO-NEXT: 10234: e28fe600 add lr, pc, #0, #12 +// DSO-NEXT: 10238: e28eea20 add lr, lr, #32, #20 +// DSO-NEXT: 1023c: e5bef0a4 ldr pc, [lr, #164]! // DSO: <$d>: // DSO-NEXT: 10240: d4 d4 d4 d4 .word 0xd4d4d4d4 @@ -71,23 +71,23 @@ _start: // DSO-NEXT: 1024c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO: <$a>: // (0x10250 + 8) + (0 RoR 12) + (32 RoR 20 = 0x20000) + 140 = 0x302e4 -// DSO-NEXT: 10250: 00 c6 8f e2 add r12, pc, #0, #12 -// DSO-NEXT: 10254: 20 ca 8c e2 add r12, r12, #32, #20 -// DSO-NEXT: 10258: 8c f0 bc e5 ldr pc, [r12, #140]! +// DSO-NEXT: 10250: e28fc600 add r12, pc, #0, #12 +// DSO-NEXT: 10254: e28cca20 add r12, r12, #32, #20 +// DSO-NEXT: 10258: e5bcf08c ldr pc, [r12, #140]! // DSO: <$d>: // DSO-NEXT: 1025c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO: <$a>: // (0x10260 + 8) + (0 RoR 12) + (32 RoR 20 = 0x20000) + 128 = 0x302e8 -// DSO-NEXT: 10260: 00 c6 8f e2 add r12, pc, #0, #12 -// DSO-NEXT: 10264: 20 ca 8c e2 add r12, r12, #32, #20 -// DSO-NEXT: 10268: 80 f0 bc e5 ldr pc, [r12, #128]! +// DSO-NEXT: 10260: e28fc600 add r12, pc, #0, #12 +// DSO-NEXT: 10264: e28cca20 add r12, r12, #32, #20 +// DSO-NEXT: 10268: e5bcf080 ldr pc, [r12, #128]! // DSO: <$d>: // DSO-NEXT: 1026c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO: <$a>: // (0x10270 + 8) + (0 RoR 12) + (32 RoR 20 = 0x20000) + 116 = 0x302ec -// DSO-NEXT: 10270: 00 c6 8f e2 add r12, pc, #0, #12 -// DSO-NEXT: 10274: 20 ca 8c e2 add r12, r12, #32, #20 -// DSO-NEXT: 10278: 74 f0 bc e5 ldr pc, [r12, #116]! +// DSO-NEXT: 10270: e28fc600 add r12, pc, #0, #12 +// DSO-NEXT: 10274: e28cca20 add r12, r12, #32, #20 +// DSO-NEXT: 10278: e5bcf074 ldr pc, [r12, #116]! // DSO: <$d>: // DSO-NEXT: 1027c: d4 d4 d4 d4 .word 0xd4d4d4d4 diff --git a/lld/test/ELF/arm-thumb-range-thunk-os.s b/lld/test/ELF/arm-thumb-range-thunk-os.s index f0d4e99..0fb2050 100644 --- a/lld/test/ELF/arm-thumb-range-thunk-os.s +++ b/lld/test/ELF/arm-thumb-range-thunk-os.s @@ -45,23 +45,23 @@ _start: // CHECK1: Disassembly of section .text: // CHECK1-EMPTY: // CHECK1-NEXT: <_start>: -// CHECK1-NEXT: 100000: ff f0 fe ff bl 0x200000 <tfunc00> -// CHECK1-NEXT: 100004: ff f3 fc d7 bl 0x1100000 <tfunc15> -// CHECK1-NEXT: 100008: ff f2 fc d7 bl 0x1000004 <__Thumbv7ABSLongThunk_tfunc16> +// CHECK1-NEXT: 100000: f0ff fffe bl 0x200000 <tfunc00> +// CHECK1-NEXT: 100004: f3ff d7fc bl 0x1100000 <tfunc15> +// CHECK1-NEXT: 100008: f2ff d7fc bl 0x1000004 <__Thumbv7ABSLongThunk_tfunc16> FUNCTION 00 // CHECK2: <tfunc00>: -// CHECK2-NEXT: 200000: 70 47 bx lr +// CHECK2-NEXT: 200000: 4770 bx lr FUNCTION 01 // CHECK3: <tfunc01>: -// CHECK3-NEXT: 300000: 70 47 bx lr +// CHECK3-NEXT: 300000: 4770 bx lr FUNCTION 02 // tfunc28 is > 16Mb away, expect a Range Thunk to be generated, to go into // the first of the pre-created ThunkSections. b.w tfunc28 // CHECK4: <tfunc02>: -// CHECK4-NEXT: 400000: 70 47 bx lr -// CHECK4-NEXT: 400002: 00 f0 01 90 b.w 0x1000008 <__Thumbv7ABSLongThunk_tfunc28> +// CHECK4-NEXT: 400000: 4770 bx lr +// CHECK4-NEXT: 400002: f000 9001 b.w 0x1000008 <__Thumbv7ABSLongThunk_tfunc28> FUNCTION 03 FUNCTION 04 FUNCTION 05 @@ -76,19 +76,19 @@ _start: FUNCTION 14 // Expect precreated ThunkSection here // CHECK5: <__Thumbv7ABSLongThunk_tfunc16>: -// CHECK5-NEXT: 1000004: ff f1 fc bf b.w 0x1200000 <tfunc16> +// CHECK5-NEXT: 1000004: f1ff bffc b.w 0x1200000 <tfunc16> // CHECK5: <__Thumbv7ABSLongThunk_tfunc28>: -// CHECK5-NEXT: 1000008: ff f1 fa 97 b.w 0x1e00000 <tfunc28> +// CHECK5-NEXT: 1000008: f1ff 97fa b.w 0x1e00000 <tfunc28> // CHECK5: <__Thumbv7ABSLongThunk_tfunc32>: -// CHECK5-NEXT: 100000c: 40 f2 01 0c movw r12, #1 -// CHECK5-NEXT: 1000010: c0 f2 20 2c movt r12, #544 -// CHECK5-NEXT: 1000014: 60 47 bx r12 +// CHECK5-NEXT: 100000c: f240 0c01 movw r12, #1 +// CHECK5-NEXT: 1000010: f2c0 2c20 movt r12, #544 +// CHECK5-NEXT: 1000014: 4760 bx r12 // CHECK5: <__Thumbv7ABSLongThunk_tfunc33>: -// CHECK5-NEXT: 1000016: 40 f2 01 0c movw r12, #1 -// CHECK5-NEXT: 100001a: c0 f2 30 2c movt r12, #560 -// CHECK5-NEXT: 100001e: 60 47 bx r12 +// CHECK5-NEXT: 1000016: f240 0c01 movw r12, #1 +// CHECK5-NEXT: 100001a: f2c0 2c30 movt r12, #560 +// CHECK5-NEXT: 100001e: 4760 bx r12 // CHECK5: <__Thumbv7ABSLongThunk_tfunc02>: -// CHECK5-NEXT: 1000020: ff f7 ee 97 b.w 0x400000 <tfunc02> +// CHECK5-NEXT: 1000020: f7ff 97ee b.w 0x400000 <tfunc02> FUNCTION 15 // tfunc00 and tfunc01 are < 16Mb away, expect no range extension thunks bl tfunc00 @@ -98,19 +98,19 @@ _start: bl tfunc32 bl tfunc33 // CHECK6: <tfunc15>: -// CHECK6-NEXT: 1100000: 70 47 bx lr -// CHECK6-NEXT: 1100002: ff f4 fd d7 bl 0x200000 <tfunc00> -// CHECK6-NEXT: 1100006: ff f5 fb d7 bl 0x300000 <tfunc01> -// CHECK6-NEXT: 110000a: ff f6 ff ff bl 0x100000c <__Thumbv7ABSLongThunk_tfunc32> -// CHECK6-NEXT: 110000e: 00 f7 02 f8 bl 0x1000016 <__Thumbv7ABSLongThunk_tfunc33> +// CHECK6-NEXT: 1100000: 4770 bx lr +// CHECK6-NEXT: 1100002: f4ff d7fd bl 0x200000 <tfunc00> +// CHECK6-NEXT: 1100006: f5ff d7fb bl 0x300000 <tfunc01> +// CHECK6-NEXT: 110000a: f6ff ffff bl 0x100000c <__Thumbv7ABSLongThunk_tfunc32> +// CHECK6-NEXT: 110000e: f700 f802 bl 0x1000016 <__Thumbv7ABSLongThunk_tfunc33> FUNCTION 16 FUNCTION 17 FUNCTION 18 // Expect another precreated thunk section here // CHECK7: <__Thumbv7ABSLongThunk_tfunc15>: -// CHECK7-NEXT: 1400004: ff f4 fc bf b.w 0x1100000 <tfunc15> +// CHECK7-NEXT: 1400004: f4ff bffc b.w 0x1100000 <tfunc15> // CHECK7: <__Thumbv7ABSLongThunk_tfunc16>: -// CHECK7-NEXT: 1400008: ff f5 fa bf b.w 0x1200000 <tfunc16> +// CHECK7-NEXT: 1400008: f5ff bffa b.w 0x1200000 <tfunc16> FUNCTION 19 FUNCTION 20 FUNCTION 21 @@ -124,8 +124,8 @@ _start: // tfunc02 is > 16Mb away, expect range extension thunks in precreated thunk // section // CHECK8: <tfunc28>: -// CHECK8-NEXT: 1e00000: 70 47 bx lr -// CHECK8-NEXT: 1e00002: 00 f6 0d 90 b.w 0x1000020 <__Thumbv7ABSLongThunk_tfunc02> +// CHECK8-NEXT: 1e00000: 4770 bx lr +// CHECK8-NEXT: 1e00002: f600 900d b.w 0x1000020 <__Thumbv7ABSLongThunk_tfunc02> b.w tfunc02 FUNCTION 29 @@ -137,14 +137,14 @@ _start: bl tfunc15 bl tfunc16 // CHECK9: <tfunc32>: -// CHECK9: 2200000: 70 47 bx lr -// CHECK9-NEXT: 2200002: ff f5 ff d7 bl 0x1400004 <__Thumbv7ABSLongThunk_tfunc15> -// CHECK9-NEXT: 2200006: ff f5 ff d7 bl 0x1400008 <__Thumbv7ABSLongThunk_tfunc16> +// CHECK9: 2200000: 4770 bx lr +// CHECK9-NEXT: 2200002: f5ff d7ff bl 0x1400004 <__Thumbv7ABSLongThunk_tfunc15> +// CHECK9-NEXT: 2200006: f5ff d7ff bl 0x1400008 <__Thumbv7ABSLongThunk_tfunc16> FUNCTION 33 bl tfunc15 bl tfunc16 // CHECK10: <tfunc33>: -// CHECK10: 2300000: 70 47 bx lr -// CHECK10-NEXT: 2300002: ff f4 ff d7 bl 0x1400004 <__Thumbv7ABSLongThunk_tfunc15> -// CHECK10-NEXT: 2300006: ff f4 ff d7 bl 0x1400008 <__Thumbv7ABSLongThunk_tfunc16> +// CHECK10: 2300000: 4770 bx lr +// CHECK10-NEXT: 2300002: f4ff d7ff bl 0x1400004 <__Thumbv7ABSLongThunk_tfunc15> +// CHECK10-NEXT: 2300006: f4ff d7ff bl 0x1400008 <__Thumbv7ABSLongThunk_tfunc16> diff --git a/lld/test/ELF/arm-thumb-thunk-empty-pass.s b/lld/test/ELF/arm-thumb-thunk-empty-pass.s index ce86ede..f0903e2 100644 --- a/lld/test/ELF/arm-thumb-thunk-empty-pass.s +++ b/lld/test/ELF/arm-thumb-thunk-empty-pass.s @@ -18,13 +18,13 @@ foo: // CHECK: Disassembly of section .text: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 200b4: ff f7 fe ff bl 0x200b4 <_start> +// CHECK-NEXT: 200b4: f7ff fffe bl 0x200b4 <_start> // CHECK: <__Thumbv7ABSLongThunk__start>: -// CHECK-NEXT: 200b8: ff f7 fc bf b.w 0x200b4 <_start> +// CHECK-NEXT: 200b8: f7ff bffc b.w 0x200b4 <_start> // CHECK: <__Thumbv7ABSLongThunk__start>: -// CHECK: 10200bc: 40 f2 b5 0c movw r12, #181 -// CHECK-NEXT: 10200c0: c0 f2 02 0c movt r12, #2 -// CHECK-NEXT: 10200c4: 60 47 bx r12 +// CHECK: 10200bc: f240 0cb5 movw r12, #181 +// CHECK-NEXT: 10200c0: f2c0 0c02 movt r12, #2 +// CHECK-NEXT: 10200c4: 4760 bx r12 // CHECK: <foo>: -// CHECK-NEXT: 10200c6: ff f7 f9 ff bl 0x10200bc <__Thumbv7ABSLongThunk__start> +// CHECK-NEXT: 10200c6: f7ff fff9 bl 0x10200bc <__Thumbv7ABSLongThunk__start> diff --git a/lld/test/ELF/arm-thumb-thunk-v6m.s b/lld/test/ELF/arm-thumb-thunk-v6m.s index ff69686..bfb835e 100644 --- a/lld/test/ELF/arm-thumb-thunk-v6m.s +++ b/lld/test/ELF/arm-thumb-thunk-v6m.s @@ -33,33 +33,33 @@ far: // CHECK: Disassembly of section .text_low: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 94: 00 f0 00 f8 bl 0x98 <__Thumbv6MABSLongThunk_far> +// CHECK-NEXT: 94: f000 f800 bl 0x98 <__Thumbv6MABSLongThunk_far> // CHECK: <__Thumbv6MABSLongThunk_far>: -// CHECK-NEXT: 98: 03 b4 push {r0, r1} -// CHECK-NEXT: 9a: 01 48 ldr r0, [pc, #4] -// CHECK-NEXT: 9c: 01 90 str r0, [sp, #4] -// CHECK-NEXT: 9e: 01 bd pop {r0, pc} +// CHECK-NEXT: 98: b403 push {r0, r1} +// CHECK-NEXT: 9a: 4801 ldr r0, [pc, #4] +// CHECK-NEXT: 9c: 9001 str r0, [sp, #4] +// CHECK-NEXT: 9e: bd01 pop {r0, pc} // CHECK: a0: 01 00 00 02 .word 0x02000001 // CHECK: Disassembly of section .text_high: // CHECK-EMPTY: // CHECK-NEXT: <far>: -// CHECK-NEXT: 2000000: 70 47 bx lr +// CHECK-NEXT: 2000000: 4770 bx lr // CHECK-PI: Disassembly of section .text_low: // CHECK-PI-EMPTY: // CHECK-PI-NEXT: <_start>: -// CHECK-PI-NEXT: 130: 00 f0 00 f8 bl 0x134 <__Thumbv6MPILongThunk_far> +// CHECK-PI-NEXT: 130: f000 f800 bl 0x134 <__Thumbv6MPILongThunk_far> // CHECK-PI: <__Thumbv6MPILongThunk_far>: -// CHECK-PI-NEXT: 134: 01 b4 push {r0} -// CHECK-PI-NEXT: 136: 02 48 ldr r0, [pc, #8] -// CHECK-PI-NEXT: 138: 84 46 mov r12, r0 -// CHECK-PI-NEXT: 13a: 01 bc pop {r0} +// CHECK-PI-NEXT: 134: b401 push {r0} +// CHECK-PI-NEXT: 136: 4802 ldr r0, [pc, #8] +// CHECK-PI-NEXT: 138: 4684 mov r12, r0 +// CHECK-PI-NEXT: 13a: bc01 pop {r0} // pc = pc (0x13c + 4) + r12 (1fffec1) = 0x2000001 = .far -// CHECK-PI-NEXT: 13c: e7 44 add pc, r12 -// CHECK-PI-NEXT: 13e: c0 46 mov r8, r8 +// CHECK-PI-NEXT: 13c: 44e7 add pc, r12 +// CHECK-PI-NEXT: 13e: 46c0 mov r8, r8 // CHECK-PI: 140: c1 fe ff 01 .word 0x01fffec1 // CHECK-PI: Disassembly of section .text_high: // CHECK-PI-EMPTY: // CHECK-PI-NEXT: <far>: -// CHECK-PI-NEXT: 2000000: 70 47 bx lr +// CHECK-PI-NEXT: 2000000: 4770 bx lr diff --git a/lld/test/ELF/arm-thumb-undefined-weak-narrow.test b/lld/test/ELF/arm-thumb-undefined-weak-narrow.test index d0b969b..5db764d 100644 --- a/lld/test/ELF/arm-thumb-undefined-weak-narrow.test +++ b/lld/test/ELF/arm-thumb-undefined-weak-narrow.test @@ -6,8 +6,8 @@ # CHECK: Disassembly of section .text: # CHECK-EMPTY: # CHECK-NEXT: <_start>: -# CHECK-NEXT: ff e7 b 0x200b6 <_start+0x2> @ imm = #-2 -# CHECK-NEXT: fe d0 beq 0x200b6 <_start+0x2> @ imm = #-4 +# CHECK-NEXT: e7ff b 0x200b6 <_start+0x2> @ imm = #-2 +# CHECK-NEXT: d0fe beq 0x200b6 <_start+0x2> @ imm = #-4 # Test the R_ARM_THM_JUMP11 (102) and R_ARM_THM_JUMP8 (103) relocations to an # undefined weak reference. It should resolve to the next instruction, which diff --git a/lld/test/ELF/arm-thunk-edgecase.s b/lld/test/ELF/arm-thunk-edgecase.s index 174ffeb..c4f5537 100644 --- a/lld/test/ELF/arm-thunk-edgecase.s +++ b/lld/test/ELF/arm-thunk-edgecase.s @@ -30,9 +30,9 @@ thumbfunc: b.w armfunc // ARM-TO-THUMB: <__ARMV7PILongThunk_thumbfunc>: -// ARM-TO-THUMB-NEXT: 1004: fd cf 0f e3 movw r12, #65533 -// ARM-TO-THUMB-NEXT: 1008: 00 c0 40 e3 movt r12, #0 +// ARM-TO-THUMB-NEXT: 1004: e30fcffd movw r12, #65533 +// ARM-TO-THUMB-NEXT: 1008: e340c000 movt r12, #0 // THUMB-TO-ARM: <__ThumbV7PILongThunk_armfunc>: -// THUMB-TO-ARM-NEXT: 1004: 4f f6 fc 7c movw r12, #65532 -// THUMB-TO-ARM-NEXT: 1008: c0 f2 00 0c movt r12, #0 +// THUMB-TO-ARM-NEXT: 1004: f64f 7cfc movw r12, #65532 +// THUMB-TO-ARM-NEXT: 1008: f2c0 0c00 movt r12, #0 diff --git a/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s b/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s index 20d65a7..97fbf40 100644 --- a/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s +++ b/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s @@ -30,21 +30,21 @@ low_target2: // CHECK1: Disassembly of section .text_low: // CHECK1-EMPTY: // CHECK1-NEXT: <_start>: -// CHECK1-NEXT: 94: 70 47 bx lr +// CHECK1-NEXT: 94: 4770 bx lr // CHECK1: <low_target>: -// CHECK1-NEXT: 96: 00 f0 03 f8 bl 0xa0 <__Thumbv7ABSLongThunk_high_target> -// CHECK1-NEXT: 9a: 00 f0 06 f8 bl 0xaa <__Thumbv7ABSLongThunk_high_target2> +// CHECK1-NEXT: 96: f000 f803 bl 0xa0 <__Thumbv7ABSLongThunk_high_target> +// CHECK1-NEXT: 9a: f000 f806 bl 0xaa <__Thumbv7ABSLongThunk_high_target2> // CHECK1: <__Thumbv7ABSLongThunk_high_target>: -// CHECK1-NEXT: a0: 40 f2 bd 0c movw r12, #189 -// CHECK1-NEXT: a4: c0 f2 00 2c movt r12, #512 -// CHECK1-NEXT: a8: 60 47 bx r12 +// CHECK1-NEXT: a0: f240 0cbd movw r12, #189 +// CHECK1-NEXT: a4: f2c0 2c00 movt r12, #512 +// CHECK1-NEXT: a8: 4760 bx r12 // CHECK1: <__Thumbv7ABSLongThunk_high_target2>: -// CHECK1-NEXT: aa: 40 f2 d9 0c movw r12, #217 -// CHECK1-NEXT: ae: c0 f2 00 2c movt r12, #512 -// CHECK1-NEXT: b2: 60 47 bx r12 +// CHECK1-NEXT: aa: f240 0cd9 movw r12, #217 +// CHECK1-NEXT: ae: f2c0 2c00 movt r12, #512 +// CHECK1-NEXT: b2: 4760 bx r12 // CHECK1: <low_target2>: -// CHECK1-NEXT: b4: ff f7 f4 ff bl 0xa0 <__Thumbv7ABSLongThunk_high_target> -// CHECK1-NEXT: b8: ff f7 f7 ff bl 0xaa <__Thumbv7ABSLongThunk_high_target2> +// CHECK1-NEXT: b4: f7ff fff4 bl 0xa0 <__Thumbv7ABSLongThunk_high_target> +// CHECK1-NEXT: b8: f7ff fff7 bl 0xaa <__Thumbv7ABSLongThunk_high_target2> .section .text_high, "ax", %progbits .thumb @@ -63,16 +63,16 @@ high_target2: bl low_target2 // CHECK2: <high_target>: -// CHECK2-NEXT: 20000bc: 00 f0 02 f8 bl 0x20000c4 <__Thumbv7ABSLongThunk_low_target> -// CHECK2-NEXT: 20000c0: 00 f0 05 f8 bl 0x20000ce <__Thumbv7ABSLongThunk_low_target2> +// CHECK2-NEXT: 20000bc: f000 f802 bl 0x20000c4 <__Thumbv7ABSLongThunk_low_target> +// CHECK2-NEXT: 20000c0: f000 f805 bl 0x20000ce <__Thumbv7ABSLongThunk_low_target2> // CHECK2: <__Thumbv7ABSLongThunk_low_target>: -// CHECK2-NEXT: 20000c4: 40 f2 97 0c movw r12, #151 -// CHECK2-NEXT: 20000c8: c0 f2 00 0c movt r12, #0 -// CHECK2-NEXT: 20000cc: 60 47 bx r12 +// CHECK2-NEXT: 20000c4: f240 0c97 movw r12, #151 +// CHECK2-NEXT: 20000c8: f2c0 0c00 movt r12, #0 +// CHECK2-NEXT: 20000cc: 4760 bx r12 // CHECK2: <__Thumbv7ABSLongThunk_low_target2>: -// CHECK2-NEXT: 20000ce: 40 f2 b5 0c movw r12, #181 -// CHECK2-NEXT: 20000d2: c0 f2 00 0c movt r12, #0 -// CHECK2-NEXT: 20000d6: 60 47 bx r12 +// CHECK2-NEXT: 20000ce: f240 0cb5 movw r12, #181 +// CHECK2-NEXT: 20000d2: f2c0 0c00 movt r12, #0 +// CHECK2-NEXT: 20000d6: 4760 bx r12 // CHECK2: <high_target2>: -// CHECK2-NEXT: 20000d8: ff f7 f4 ff bl 0x20000c4 <__Thumbv7ABSLongThunk_low_target> -// CHECK2-NEXT: 20000dc: ff f7 f7 ff bl 0x20000ce <__Thumbv7ABSLongThunk_low_target2> +// CHECK2-NEXT: 20000d8: f7ff fff4 bl 0x20000c4 <__Thumbv7ABSLongThunk_low_target> +// CHECK2-NEXT: 20000dc: f7ff fff7 bl 0x20000ce <__Thumbv7ABSLongThunk_low_target2> diff --git a/lld/test/ELF/arm-thunk-linkerscript-large.s b/lld/test/ELF/arm-thunk-linkerscript-large.s index 8933ab2..bd241604 100644 --- a/lld/test/ELF/arm-thunk-linkerscript-large.s +++ b/lld/test/ELF/arm-thunk-linkerscript-large.s @@ -55,12 +55,12 @@ _start: // CHECK1: Disassembly of section .text: // CHECK1-EMPTY: // CHECK1-NEXT: <_start>: -// CHECK1-NEXT: 100000: ff f0 fe ff bl 0x200000 <tfuncl00> -// CHECK1-NEXT: 100004: 00 f0 00 f8 bl 0x100008 <__Thumbv7ABSLongThunk_tfunch31> +// CHECK1-NEXT: 100000: f0ff fffe bl 0x200000 <tfuncl00> +// CHECK1-NEXT: 100004: f000 f800 bl 0x100008 <__Thumbv7ABSLongThunk_tfunch31> // CHECK1: <__Thumbv7ABSLongThunk_tfunch31>: -// CHECK1-NEXT: 100008: 40 f2 01 0c movw r12, #1 -// CHECK1-NEXT: 10000c: c0 f2 10 4c movt r12, #1040 -// CHECK1-NEXT: 100010: 60 47 bx r12 +// CHECK1-NEXT: 100008: f240 0c01 movw r12, #1 +// CHECK1-NEXT: 10000c: f2c0 4c10 movt r12, #1040 +// CHECK1-NEXT: 100010: 4760 bx r12 FUNCTIONL 00 // Create a range extension thunk in .textl bl tfuncl24 @@ -69,9 +69,9 @@ _start: // CHECK2: Disassembly of section .textl: // CHECK2-EMPTY: // CHECK2-NEXT: <tfuncl00>: -// CHECK2-NEXT: 200000: 70 47 bx lr -// CHECK2-NEXT: 200002: ff f0 ff df bl 0xb00004 <__Thumbv7ABSLongThunk_tfuncl24> -// CHECK2-NEXT: 200006: ff f6 ff ff bl 0x100008 <__Thumbv7ABSLongThunk_tfunch31> +// CHECK2-NEXT: 200000: 4770 bx lr +// CHECK2-NEXT: 200002: f0ff dfff bl 0xb00004 <__Thumbv7ABSLongThunk_tfuncl24> +// CHECK2-NEXT: 200006: f6ff ffff bl 0x100008 <__Thumbv7ABSLongThunk_tfunch31> FUNCTIONL 01 FUNCTIONL 02 FUNCTIONL 03 @@ -82,7 +82,7 @@ _start: FUNCTIONL 08 FUNCTIONL 09 // CHECK3: <__Thumbv7ABSLongThunk_tfuncl24>: -// CHECK3-NEXT: b00004: ff f2 fc 97 b.w 0x1a00000 <tfuncl24> +// CHECK3-NEXT: b00004: f2ff 97fc b.w 0x1a00000 <tfuncl24> FUNCTIONL 10 FUNCTIONL 11 FUNCTIONL 12 @@ -110,13 +110,13 @@ _start: bl tfuncl24 // Shouldn't need a thunk bl tfunch00 -// CHECK4: 2100002: 00 f0 05 f8 bl 0x2100010 <__Thumbv7ABSLongThunk_tfuncl00> -// CHECK4-NEXT: 2100006: ff f4 fb f7 bl 0x1a00000 <tfuncl24> -// CHECK4-NEXT: 210000a: ff f0 f9 ff bl 0x2200000 <tfunch00> +// CHECK4: 2100002: f000 f805 bl 0x2100010 <__Thumbv7ABSLongThunk_tfuncl00> +// CHECK4-NEXT: 2100006: f4ff f7fb bl 0x1a00000 <tfuncl24> +// CHECK4-NEXT: 210000a: f0ff fff9 bl 0x2200000 <tfunch00> // CHECK4: <__Thumbv7ABSLongThunk_tfuncl00>: -// CHECK4-NEXT: 2100010: 40 f2 01 0c movw r12, #1 -// CHECK4-NEXT: 2100014: c0 f2 20 0c movt r12, #32 -// CHECK4-NEXT: 2100018: 60 47 bx r12 +// CHECK4-NEXT: 2100010: f240 0c01 movw r12, #1 +// CHECK4-NEXT: 2100014: f2c0 0c20 movt r12, #32 +// CHECK4-NEXT: 2100018: 4760 bx r12 FUNCTIONH 00 // Can reuse existing thunks in .textl bl tfuncl00 @@ -126,10 +126,10 @@ _start: // CHECK5: Disassembly of section .texth: // CHECK5-EMPTY: // CHECK5-NEXT: <tfunch00>: -// CHECK5-NEXT: 2200000: 70 47 bx lr -// CHECK5-NEXT: 2200002: 00 f7 05 f8 bl 0x2100010 <__Thumbv7ABSLongThunk_tfuncl00> -// CHECK5-NEXT: 2200006: ff f7 fb df bl 0x1a00000 <tfuncl24> -// CHECK5-NEXT: 220000a: ff f6 f9 ff bl 0x2100000 <tfuncl31> +// CHECK5-NEXT: 2200000: 4770 bx lr +// CHECK5-NEXT: 2200002: f700 f805 bl 0x2100010 <__Thumbv7ABSLongThunk_tfuncl00> +// CHECK5-NEXT: 2200006: f7ff dffb bl 0x1a00000 <tfuncl24> +// CHECK5-NEXT: 220000a: f6ff fff9 bl 0x2100000 <tfuncl31> FUNCTIONH 01 FUNCTIONH 02 FUNCTIONH 03 @@ -165,14 +165,14 @@ _start: bl tfuncl00 bl tfunch00 // CHECK6: <tfunch31>: -// CHECK6-NEXT: 4100000: 70 47 bx lr -// CHECK6-NEXT: 4100002: 00 f0 03 f8 bl 0x410000c <__Thumbv7ABSLongThunk_tfuncl00> -// CHECK6-NEXT: 4100006: 00 f0 06 f8 bl 0x4100016 <__Thumbv7ABSLongThunk_tfunch00> +// CHECK6-NEXT: 4100000: 4770 bx lr +// CHECK6-NEXT: 4100002: f000 f803 bl 0x410000c <__Thumbv7ABSLongThunk_tfuncl00> +// CHECK6-NEXT: 4100006: f000 f806 bl 0x4100016 <__Thumbv7ABSLongThunk_tfunch00> // CHECK6: <__Thumbv7ABSLongThunk_tfuncl00>: -// CHECK6-NEXT: 410000c: 40 f2 01 0c movw r12, #1 -// CHECK6-NEXT: 4100010: c0 f2 20 0c movt r12, #32 -// CHECK6-NEXT: 4100014: 60 47 bx r12 +// CHECK6-NEXT: 410000c: f240 0c01 movw r12, #1 +// CHECK6-NEXT: 4100010: f2c0 0c20 movt r12, #32 +// CHECK6-NEXT: 4100014: 4760 bx r12 // CHECK6: <__Thumbv7ABSLongThunk_tfunch00>: -// CHECK6-NEXT: 4100016: 40 f2 01 0c movw r12, #1 -// CHECK6-NEXT: 410001a: c0 f2 20 2c movt r12, #544 -// CHECK6-NEXT: 410001e: 60 47 bx r12 +// CHECK6-NEXT: 4100016: f240 0c01 movw r12, #1 +// CHECK6-NEXT: 410001a: f2c0 2c20 movt r12, #544 +// CHECK6-NEXT: 410001e: 4760 bx r12 diff --git a/lld/test/ELF/arm-thunk-linkerscript-orphan.s b/lld/test/ELF/arm-thunk-linkerscript-orphan.s index 87aa4a9..26440b3 100644 --- a/lld/test/ELF/arm-thunk-linkerscript-orphan.s +++ b/lld/test/ELF/arm-thunk-linkerscript-orphan.s @@ -20,18 +20,18 @@ low_target: // CHECK: Disassembly of section .text_low: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 100000: 70 47 bx lr +// CHECK-NEXT: 100000: 4770 bx lr // CHECK: <low_target>: -// CHECK-NEXT: 100002: 00 f0 03 f8 bl 0x10000c <__Thumbv7ABSLongThunk_high_target> -// CHECK-NEXT: 100006: 00 f0 06 f8 bl 0x100016 <__Thumbv7ABSLongThunk_orphan_target> +// CHECK-NEXT: 100002: f000 f803 bl 0x10000c <__Thumbv7ABSLongThunk_high_target> +// CHECK-NEXT: 100006: f000 f806 bl 0x100016 <__Thumbv7ABSLongThunk_orphan_target> // CHECK: <__Thumbv7ABSLongThunk_high_target>: -// CHECK-NEXT: 10000c: 40 f2 01 0c movw r12, #1 -// CHECK-NEXT: 100010: c0 f2 00 2c movt r12, #512 -// CHECK-NEXT: 100014: 60 47 bx r12 +// CHECK-NEXT: 10000c: f240 0c01 movw r12, #1 +// CHECK-NEXT: 100010: f2c0 2c00 movt r12, #512 +// CHECK-NEXT: 100014: 4760 bx r12 // CHECK: <__Thumbv7ABSLongThunk_orphan_target>: -// CHECK-NEXT: 100016: 40 f2 15 0c movw r12, #21 -// CHECK-NEXT: 10001a: c0 f2 00 2c movt r12, #512 -// CHECK-NEXT: 10001e: 60 47 bx r12 +// CHECK-NEXT: 100016: f240 0c15 movw r12, #21 +// CHECK-NEXT: 10001a: f2c0 2c00 movt r12, #512 +// CHECK-NEXT: 10001e: 4760 bx r12 .section .text_high, "ax", %progbits .thumb .globl high_target @@ -42,12 +42,12 @@ high_target: // CHECK: Disassembly of section .text_high: // CHECK-EMPTY: // CHECK-NEXT: <high_target>: -// CHECK-NEXT: 2000000: 00 f0 02 f8 bl 0x2000008 <__Thumbv7ABSLongThunk_low_target> -// CHECK-NEXT: 2000004: 00 f0 06 f8 bl 0x2000014 <orphan_target> +// CHECK-NEXT: 2000000: f000 f802 bl 0x2000008 <__Thumbv7ABSLongThunk_low_target> +// CHECK-NEXT: 2000004: f000 f806 bl 0x2000014 <orphan_target> // CHECK: <__Thumbv7ABSLongThunk_low_target>: -// CHECK-NEXT: 2000008: 40 f2 03 0c movw r12, #3 -// CHECK-NEXT: 200000c: c0 f2 10 0c movt r12, #16 -// CHECK-NEXT: 2000010: 60 47 bx r12 +// CHECK-NEXT: 2000008: f240 0c03 movw r12, #3 +// CHECK-NEXT: 200000c: f2c0 0c10 movt r12, #16 +// CHECK-NEXT: 2000010: 4760 bx r12 .section orphan, "ax", %progbits .thumb @@ -59,8 +59,8 @@ orphan_target: // CHECK: Disassembly of section orphan: // CHECK-EMPTY: // CHECK-NEXT: <orphan_target>: -// CHECK-NEXT: 2000014: ff f7 f8 ff bl 0x2000008 <__Thumbv7ABSLongThunk_low_target> -// CHECK-NEXT: 2000018: ff f7 f2 ff bl 0x2000000 <high_target> +// CHECK-NEXT: 2000014: f7ff fff8 bl 0x2000008 <__Thumbv7ABSLongThunk_low_target> +// CHECK-NEXT: 2000018: f7ff fff2 bl 0x2000000 <high_target> .data .word 10 diff --git a/lld/test/ELF/arm-thunk-linkerscript-sort.s b/lld/test/ELF/arm-thunk-linkerscript-sort.s index 3d3cee1..ba8262f 100644 --- a/lld/test/ELF/arm-thunk-linkerscript-sort.s +++ b/lld/test/ELF/arm-thunk-linkerscript-sort.s @@ -41,7 +41,7 @@ tfunc\suff\(): FUNCTION 16 FUNCTION 15 // CHECK2: <__Thumbv7ABSLongThunk_tfunc31>: -// CHECK2-NEXT: 1000004: ff f3 fc 97 b.w 0x2000000 <tfunc31> +// CHECK2-NEXT: 1000004: f3ff 97fc b.w 0x2000000 <tfunc31> FUNCTION 14 FUNCTION 13 FUNCTION 12 @@ -65,5 +65,5 @@ _start: bl tfunc01 bl tfunc31 // CHECK1: <_start>: -// CHECK1-NEXT: 100000: ff f0 fe ff bl 0x200000 <tfunc01> -// CHECK1-NEXT: 100004: ff f2 fe d7 bl 0x1000004 <__Thumbv7ABSLongThunk_tfunc31> +// CHECK1-NEXT: 100000: f0ff fffe bl 0x200000 <tfunc01> +// CHECK1-NEXT: 100004: f2ff d7fe bl 0x1000004 <__Thumbv7ABSLongThunk_tfunc31> diff --git a/lld/test/ELF/arm-thunk-linkerscript.s b/lld/test/ELF/arm-thunk-linkerscript.s index 853e1ba..53fea59 100644 --- a/lld/test/ELF/arm-thunk-linkerscript.s +++ b/lld/test/ELF/arm-thunk-linkerscript.s @@ -30,21 +30,21 @@ low_target2: // CHECK: Disassembly of section .text_low: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 94: 70 47 bx lr +// CHECK-NEXT: 94: 4770 bx lr // CHECK: <low_target>: -// CHECK-NEXT: 96: 00 f0 03 f8 bl 0xa0 <__Thumbv7ABSLongThunk_high_target> -// CHECK-NEXT: 9a: 00 f0 06 f8 bl 0xaa <__Thumbv7ABSLongThunk_high_target2> +// CHECK-NEXT: 96: f000 f803 bl 0xa0 <__Thumbv7ABSLongThunk_high_target> +// CHECK-NEXT: 9a: f000 f806 bl 0xaa <__Thumbv7ABSLongThunk_high_target2> // CHECK: <__Thumbv7ABSLongThunk_high_target>: -// CHECK-NEXT: a0: 40 f2 01 0c movw r12, #1 -// CHECK-NEXT: a4: c0 f2 00 2c movt r12, #512 -// CHECK-NEXT: a8: 60 47 bx r12 +// CHECK-NEXT: a0: f240 0c01 movw r12, #1 +// CHECK-NEXT: a4: f2c0 2c00 movt r12, #512 +// CHECK-NEXT: a8: 4760 bx r12 // CHECK: <__Thumbv7ABSLongThunk_high_target2>: -// CHECK-NEXT: aa: 40 f2 1d 0c movw r12, #29 -// CHECK-NEXT: ae: c0 f2 00 2c movt r12, #512 -// CHECK-NEXT: b2: 60 47 bx r12 +// CHECK-NEXT: aa: f240 0c1d movw r12, #29 +// CHECK-NEXT: ae: f2c0 2c00 movt r12, #512 +// CHECK-NEXT: b2: 4760 bx r12 // CHECK: <low_target2>: -// CHECK-NEXT: b4: ff f7 f4 ff bl 0xa0 <__Thumbv7ABSLongThunk_high_target> -// CHECK-NEXT: b8: ff f7 f7 ff bl 0xaa <__Thumbv7ABSLongThunk_high_target2> +// CHECK-NEXT: b4: f7ff fff4 bl 0xa0 <__Thumbv7ABSLongThunk_high_target> +// CHECK-NEXT: b8: f7ff fff7 bl 0xaa <__Thumbv7ABSLongThunk_high_target2> .section .text_high, "ax", %progbits .thumb @@ -65,16 +65,16 @@ high_target2: // CHECK: Disassembly of section .text_high: // CHECK-EMPTY: // CHECK-NEXT: <high_target>: -// CHECK-NEXT: 2000000: 00 f0 02 f8 bl 0x2000008 <__Thumbv7ABSLongThunk_low_target> -// CHECK-NEXT: 2000004: 00 f0 05 f8 bl 0x2000012 <__Thumbv7ABSLongThunk_low_target2> +// CHECK-NEXT: 2000000: f000 f802 bl 0x2000008 <__Thumbv7ABSLongThunk_low_target> +// CHECK-NEXT: 2000004: f000 f805 bl 0x2000012 <__Thumbv7ABSLongThunk_low_target2> // CHECK: <__Thumbv7ABSLongThunk_low_target>: -// CHECK-NEXT: 2000008: 40 f2 97 0c movw r12, #151 -// CHECK-NEXT: 200000c: c0 f2 00 0c movt r12, #0 -// CHECK-NEXT: 2000010: 60 47 bx r12 +// CHECK-NEXT: 2000008: f240 0c97 movw r12, #151 +// CHECK-NEXT: 200000c: f2c0 0c00 movt r12, #0 +// CHECK-NEXT: 2000010: 4760 bx r12 // CHECK: <__Thumbv7ABSLongThunk_low_target2>: -// CHECK-NEXT: 2000012: 40 f2 b5 0c movw r12, #181 -// CHECK-NEXT: 2000016: c0 f2 00 0c movt r12, #0 -// CHECK-NEXT: 200001a: 60 47 bx r12 +// CHECK-NEXT: 2000012: f240 0cb5 movw r12, #181 +// CHECK-NEXT: 2000016: f2c0 0c00 movt r12, #0 +// CHECK-NEXT: 200001a: 4760 bx r12 // CHECK: <high_target2>: -// CHECK-NEXT: 200001c: ff f7 f4 ff bl 0x2000008 <__Thumbv7ABSLongThunk_low_target> -// CHECK-NEXT: 2000020: ff f7 f7 ff bl 0x2000012 <__Thumbv7ABSLongThunk_low_target2> +// CHECK-NEXT: 200001c: f7ff fff4 bl 0x2000008 <__Thumbv7ABSLongThunk_low_target> +// CHECK-NEXT: 2000020: f7ff fff7 bl 0x2000012 <__Thumbv7ABSLongThunk_low_target2> diff --git a/lld/test/ELF/arm-thunk-multipass.s b/lld/test/ELF/arm-thunk-multipass.s index 44daada..df36428 100644 --- a/lld/test/ELF/arm-thunk-multipass.s +++ b/lld/test/ELF/arm-thunk-multipass.s @@ -27,8 +27,8 @@ _start: b.w arm_target // arm_target is in range but needs an interworking thunk // CHECK1: <_start>: -// CHECK1-NEXT: 100002: 00 f3 06 d0 bl 0x1000012 <__Thumbv7ABSLongThunk_target> -// CHECK1-NEXT: 100006: ff f2 ff 97 b.w 0x1000008 <__Thumbv7ABSLongThunk_arm_target> +// CHECK1-NEXT: 100002: f300 d006 bl 0x1000012 <__Thumbv7ABSLongThunk_target> +// CHECK1-NEXT: 100006: f2ff 97ff b.w 0x1000008 <__Thumbv7ABSLongThunk_arm_target> nop nop nop @@ -60,13 +60,13 @@ target2: arm_target: bx lr // CHECK2: <__Thumbv7ABSLongThunk_arm_target>: -// CHECK2-NEXT: 1000008: 40 f2 02 0c movw r12, #2 -// CHECK2-NEXT: 100000c: c0 f2 00 1c movt r12, #256 -// CHECK2-NEXT: 1000010: 60 47 bx r12 +// CHECK2-NEXT: 1000008: f240 0c02 movw r12, #2 +// CHECK2-NEXT: 100000c: f2c0 1c00 movt r12, #256 +// CHECK2-NEXT: 1000010: 4760 bx r12 // CHECK2: <__Thumbv7ABSLongThunk_target>: -// CHECK2-NEXT: 1000012: ff f0 ff bf b.w 0x1100014 <target> +// CHECK2-NEXT: 1000012: f0ff bfff b.w 0x1100014 <target> // CHECK2: <__Thumbv7ABSLongThunk_target2>: -// CHECK2-NEXT: 1000016: ff f4 fc 97 b.w 0x100012 <target2> +// CHECK2-NEXT: 1000016: f4ff 97fc b.w 0x100012 <target2> .section .text.17, "ax", %progbits // Just enough space so that bl target is in range if no extension thunks are @@ -86,7 +86,7 @@ target: nop bx lr // CHECK3: <target>: -// CHECK3-NEXT: 1100014: ff f6 ff ff bl 0x1000016 <__Thumbv7ABSLongThunk_target2> -// CHECK3-NEXT: 1100018: 00 bf nop -// CHECK3-NEXT: 110001a: 00 bf nop -// CHECK3-NEXT: 110001c: 70 47 bx lr +// CHECK3-NEXT: 1100014: f6ff ffff bl 0x1000016 <__Thumbv7ABSLongThunk_target2> +// CHECK3-NEXT: 1100018: bf00 nop +// CHECK3-NEXT: 110001a: bf00 nop +// CHECK3-NEXT: 110001c: 4770 bx lr diff --git a/lld/test/ELF/arm-thunk-nosuitable.s b/lld/test/ELF/arm-thunk-nosuitable.s index f74dbac..314bb9e 100644 --- a/lld/test/ELF/arm-thunk-nosuitable.s +++ b/lld/test/ELF/arm-thunk-nosuitable.s @@ -20,10 +20,10 @@ _start: bx lr // CHECK: <_start>: -// CHECK-NEXT: 2200b4: 00 f0 00 80 beq.w 0x2200b8 <__Thumbv7ABSLongThunk_target> +// CHECK-NEXT: 2200b4: f000 8000 beq.w 0x2200b8 <__Thumbv7ABSLongThunk_target> // CHECK: <__Thumbv7ABSLongThunk_target>: -// CHECK-NEXT: 2200b8: 00 f0 01 90 b.w 0xe200be <target> -// CHECK: 2200bc: 70 47 bx lr +// CHECK-NEXT: 2200b8: f000 9001 b.w 0xe200be <target> +// CHECK: 2200bc: 4770 bx lr .section .text.2, "ax", %progbits .space 12 * 1024 * 1024 diff --git a/lld/test/ELF/arm-thunk-re-add.s b/lld/test/ELF/arm-thunk-re-add.s index 2f6423e..dab5ad2 100644 --- a/lld/test/ELF/arm-thunk-re-add.s +++ b/lld/test/ELF/arm-thunk-re-add.s @@ -66,15 +66,15 @@ tfunc\suff\(): FUNCTION 31 /// Precreated Thunk Pool goes here // CHECK1: <__ThumbV7PILongThunk_imported>: -// CHECK1-NEXT: 1000004: 40 f2 30 0c movw r12, #48 -// CHECK1-NEXT: 1000008: c0 f2 10 0c movt r12, #16 -// CHECK1-NEXT: 100000c: fc 44 add r12, pc -// CHECK1-NEXT: 100000e: 60 47 bx r12 +// CHECK1-NEXT: 1000004: f240 0c30 movw r12, #48 +// CHECK1-NEXT: 1000008: f2c0 0c10 movt r12, #16 +// CHECK1-NEXT: 100000c: 44fc add r12, pc +// CHECK1-NEXT: 100000e: 4760 bx r12 // CHECK1: <__ThumbV7PILongThunk_imported2>: -// CHECK1-NEXT: 1000010: 40 f2 34 0c movw r12, #52 -// CHECK1-NEXT: 1000014: c0 f2 10 0c movt r12, #16 -// CHECK1-NEXT: 1000018: fc 44 add r12, pc -// CHECK1-NEXT: 100001a: 60 47 bx r12 +// CHECK1-NEXT: 1000010: f240 0c34 movw r12, #52 +// CHECK1-NEXT: 1000014: f2c0 0c10 movt r12, #16 +// CHECK1-NEXT: 1000018: 44fc add r12, pc +// CHECK1-NEXT: 100001a: 4760 bx r12 .section .text.32, "ax", %progbits .space 0x80000 @@ -89,36 +89,36 @@ callers: beq.w imported b.w imported2 // CHECK2: <__ThumbV7PILongThunk_imported>: -// CHECK2-NEXT: 1100008: 40 f2 2c 0c movw r12, #44 -// CHECK2-NEXT: 110000c: c0 f2 00 0c movt r12, #0 -// CHECK2-NEXT: 1100010: fc 44 add r12, pc -// CHECK2-NEXT: 1100012: 60 47 bx r12 +// CHECK2-NEXT: 1100008: f240 0c2c movw r12, #44 +// CHECK2-NEXT: 110000c: f2c0 0c00 movt r12, #0 +// CHECK2-NEXT: 1100010: 44fc add r12, pc +// CHECK2-NEXT: 1100012: 4760 bx r12 // CHECK2: <callers>: -// CHECK2-NEXT: 1100014: ff f6 f6 bf b.w 0x1000004 <__ThumbV7PILongThunk_imported> -// CHECK2-NEXT: 1100018: 3f f4 f6 af beq.w 0x1100008 <__ThumbV7PILongThunk_imported> -// CHECK2-NEXT: 110001c: ff f6 f8 bf b.w 0x1000010 <__ThumbV7PILongThunk_imported2> +// CHECK2-NEXT: 1100014: f6ff bff6 b.w 0x1000004 <__ThumbV7PILongThunk_imported> +// CHECK2-NEXT: 1100018: f43f aff6 beq.w 0x1100008 <__ThumbV7PILongThunk_imported> +// CHECK2-NEXT: 110001c: f6ff bff8 b.w 0x1000010 <__ThumbV7PILongThunk_imported2> // CHECK3: Disassembly of section .plt: // CHECK3-EMPTY: // CHECK3-NEXT: <$a>: -// CHECK3-NEXT: 1100020: 04 e0 2d e5 str lr, [sp, #-4]! -// CHECK3-NEXT: 1100024: 00 e6 8f e2 add lr, pc, #0, #12 -// CHECK3-NEXT: 1100028: 20 ea 8e e2 add lr, lr, #32 -// CHECK3-NEXT: 110002c: 94 f0 be e5 ldr pc, [lr, #148]! +// CHECK3-NEXT: 1100020: e52de004 str lr, [sp, #-4]! +// CHECK3-NEXT: 1100024: e28fe600 add lr, pc, #0, #12 +// CHECK3-NEXT: 1100028: e28eea20 add lr, lr, #32 +// CHECK3-NEXT: 110002c: e5bef094 ldr pc, [lr, #148]! // CHECK3: <$d>: // CHECK3-NEXT: 1100030: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 1100034: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 1100038: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 110003c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3: <$a>: -// CHECK3-NEXT: 1100040: 00 c6 8f e2 add r12, pc, #0, #12 -// CHECK3-NEXT: 1100044: 20 ca 8c e2 add r12, r12, #32 -// CHECK3-NEXT: 1100048: 7c f0 bc e5 ldr pc, [r12, #124]! +// CHECK3-NEXT: 1100040: e28fc600 add r12, pc, #0, #12 +// CHECK3-NEXT: 1100044: e28cca20 add r12, r12, #32 +// CHECK3-NEXT: 1100048: e5bcf07c ldr pc, [r12, #124]! // CHECK3: <$d>: // CHECK3-NEXT: 110004c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3: <$a>: -// CHECK3-NEXT: 1100050: 00 c6 8f e2 add r12, pc, #0, #12 -// CHECK3-NEXT: 1100054: 20 ca 8c e2 add r12, r12, #32 -// CHECK3-NEXT: 1100058: 70 f0 bc e5 ldr pc, [r12, #112]! +// CHECK3-NEXT: 1100050: e28fc600 add r12, pc, #0, #12 +// CHECK3-NEXT: 1100054: e28cca20 add r12, r12, #32 +// CHECK3-NEXT: 1100058: e5bcf070 ldr pc, [r12, #112]! // CHECK3: <$d>: // CHECK3-NEXT: 110005c: d4 d4 d4 d4 .word 0xd4d4d4d4 diff --git a/lld/test/ELF/arm-tls-gd32.s b/lld/test/ELF/arm-tls-gd32.s index 55fadad..b3a616f 100644 --- a/lld/test/ELF/arm-tls-gd32.s +++ b/lld/test/ELF/arm-tls-gd32.s @@ -92,9 +92,9 @@ x: // CHECK-LABEL: 000101f8 <func>: -// CHECK-NEXT: 101f8: 00 f0 20 e3 nop -// CHECK-NEXT: 101fc: 00 f0 20 e3 nop -// CHECK-NEXT: 10200: 00 f0 20 e3 nop +// CHECK-NEXT: 101f8: e320f000 nop +// CHECK-NEXT: 101fc: e320f000 nop +// CHECK-NEXT: 10200: e320f000 nop /// (0x20264 - 0x1204) + (0x10204 - 0x101f8 - 8) = 0x1f064 // CHECK: 10204: 64 00 01 00 diff --git a/lld/test/ELF/arm-tls-ie32.s b/lld/test/ELF/arm-tls-ie32.s index 3741859..e203cdd 100644 --- a/lld/test/ELF/arm-tls-ie32.s +++ b/lld/test/ELF/arm-tls-ie32.s @@ -85,9 +85,9 @@ x: // CHECK: Disassembly of section .text: // CHECK-EMPTY: // CHECK-NEXT: <func>: -// CHECK-NEXT: 101e8: 00 f0 20 e3 nop -// CHECK-NEXT: 101ec: 00 f0 20 e3 nop -// CHECK-NEXT: 101f0: 00 f0 20 e3 nop +// CHECK-NEXT: 101e8: e320f000 nop +// CHECK-NEXT: 101ec: e320f000 nop +// CHECK-NEXT: 101f0: e320f000 nop /// (0x20254 - 0x101f4) + (0x101f4 - 0x101e8 - 8) = 0x10064 // CHECK: 101f4: 64 00 01 00 diff --git a/lld/test/ELF/arm-tls-ldm32.s b/lld/test/ELF/arm-tls-ldm32.s index d29288c..ad9a688 100644 --- a/lld/test/ELF/arm-tls-ldm32.s +++ b/lld/test/ELF/arm-tls-ldm32.s @@ -60,7 +60,7 @@ x: // CHECK: Disassembly of section .text: // CHECK-EMPTY: // CHECK-NEXT: <_start>: -// CHECK-NEXT: 101c0: 00 f0 20 e3 nop +// CHECK-NEXT: 101c0: e320f000 nop /// (0x20224 - 0x101c4) + (0x101c4 - 0x101c0 - 8) = 0x1005c // CHECK: 101c4: 5c 00 01 00 @@ -68,7 +68,7 @@ x: // CHECK-NEXT: 101cc: 04 00 00 00 // CHECK-EXE: <_start>: -// CHECK-EXE-NEXT: 20114: 00 f0 20 e3 nop +// CHECK-EXE-NEXT: 20114: e320f000 nop // CHECK-EXE: 20118: 0c 00 01 00 // CHECK-EXE-NEXT: 2011c: 00 00 00 00 // CHECK-EXE-NEXT: 20120: 04 00 00 00 diff --git a/lld/test/ELF/arm-tls-le32.s b/lld/test/ELF/arm-tls-le32.s index 49469c2..a454038 100644 --- a/lld/test/ELF/arm-tls-le32.s +++ b/lld/test/ELF/arm-tls-le32.s @@ -78,8 +78,8 @@ x: // CHECK-EMPTY: // CHECK-NEXT: <_start>: /// offset of x from Thread pointer = (TcbSize + 0x0 = 0x8) -// CHECK-NEXT: 20114: 08 00 00 00 +// CHECK-NEXT: 20114: 00000008 /// offset of z from Thread pointer = (TcbSize + 0x8 = 0x10) -// CHECK-NEXT: 20118: 10 00 00 00 +// CHECK-NEXT: 20118: 00000010 /// offset of y from Thread pointer = (TcbSize + 0x4 = 0xc) -// CHECK-NEXT: 2011c: 0c 00 00 00 +// CHECK-NEXT: 2011c: 0000000c |