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author | Ties Stuij <ties.stuij@arm.com> | 2021-12-08 09:44:45 +0000 |
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committer | Ties Stuij <ties.stuij@arm.com> | 2021-12-08 09:44:45 +0000 |
commit | e6d0b851f854849240bc1f02901b0dbb3be84388 (patch) | |
tree | b8f79c546815b4364215cb48390ce19717dbb0c3 /libunwind/include | |
parent | 96b92d5b3ec43be18146a346b65cc82766cf8b3a (diff) | |
download | llvm-e6d0b851f854849240bc1f02901b0dbb3be84388.zip llvm-e6d0b851f854849240bc1f02901b0dbb3be84388.tar.gz llvm-e6d0b851f854849240bc1f02901b0dbb3be84388.tar.bz2 |
[ARM][libunwind] add PACBTI-M support for libunwind
This patch implements the following:
- Emit PACBTI-M build attributes in libunwind asm files
- Authenticate LR in DWARF32 using PACBTI
Use Armv8.1-M.Main PACBTI extension to authenticate the return address
(stored in the LR register) before moving it to the PC (IP) register.
The AUTG instruction is used with the candidate return address, the CFA,
and the authentication code that is retrieved from the saved
pseudo-register RA_AUTH_CODE.
- Authenticate LR in EHABI using PACBTI
Authenticate the contents of the LR register using Armv8.1-M.Main PACBTI
extension.
A new frame unwinding instruction is introduced (0xb4). This
instruction pops out of the stack the return address authentication
code, which is then used in conjunction with the SP and the next-to-be
instruction pointer to perform authentication.
This authentication code is popped into a new register,
UNW_ARM_PSEUDO_PAC, which is a pseudo-register.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Momchil Velikov
- Victor Campos
- Ties Stuij
Reviewed By: #libunwind, danielkiss, mstorsjo
Differential Revision: https://reviews.llvm.org/D112430
Diffstat (limited to 'libunwind/include')
-rw-r--r-- | libunwind/include/libunwind.h | 3 | ||||
-rw-r--r-- | libunwind/include/unwind_arm_ehabi.h | 7 |
2 files changed, 6 insertions, 4 deletions
diff --git a/libunwind/include/libunwind.h b/libunwind/include/libunwind.h index e187ee2..9a74faa 100644 --- a/libunwind/include/libunwind.h +++ b/libunwind/include/libunwind.h @@ -718,7 +718,8 @@ enum { UNW_ARM_WR14 = 126, UNW_ARM_WR15 = 127, // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC} - // 134-143 -- Reserved + // 134-142 -- Reserved + UNW_ARM_RA_AUTH_CODE = 143, // 144-150 -- R8_USR-R14_USR // 151-157 -- R8_FIQ-R14_FIQ // 158-159 -- R13_IRQ-R14_IRQ diff --git a/libunwind/include/unwind_arm_ehabi.h b/libunwind/include/unwind_arm_ehabi.h index dc9d403..6277a14 100644 --- a/libunwind/include/unwind_arm_ehabi.h +++ b/libunwind/include/unwind_arm_ehabi.h @@ -87,10 +87,11 @@ extern void _Unwind_Resume(_Unwind_Exception *exception_object); extern void _Unwind_DeleteException(_Unwind_Exception *exception_object); typedef enum { - _UVRSC_CORE = 0, /* integer register */ - _UVRSC_VFP = 1, /* vfp */ + _UVRSC_CORE = 0, /* integer register */ + _UVRSC_VFP = 1, /* vfp */ _UVRSC_WMMXD = 3, /* Intel WMMX data register */ - _UVRSC_WMMXC = 4 /* Intel WMMX control register */ + _UVRSC_WMMXC = 4, /* Intel WMMX control register */ + _UVRSC_PSEUDO = 5 /* Special purpose pseudo register */ } _Unwind_VRS_RegClass; typedef enum { |