diff options
| author | Manolis Tsamis <manolis.tsamis@vrull.eu> | 2023-02-21 12:21:35 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-21 12:21:49 +0100 |
| commit | bbb58a2302c65b73943e00f2def3384a68177a7f (patch) | |
| tree | dc3718c2d2e745067dbee2328299e0e44ee432c2 /libcxxabi | |
| parent | d567e06946b70136d344df3d8601c5e02cb596e1 (diff) | |
| download | llvm-bbb58a2302c65b73943e00f2def3384a68177a7f.zip llvm-bbb58a2302c65b73943e00f2def3384a68177a7f.tar.gz llvm-bbb58a2302c65b73943e00f2def3384a68177a7f.tar.bz2 | |
[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd
Depends on D143847
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144002
Diffstat (limited to 'libcxxabi')
0 files changed, 0 insertions, 0 deletions