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authorCyrill Leutwiler <bigcyrill@hotmail.com>2024-04-11 07:11:51 +0200
committerTom Stellard <tstellar@redhat.com>2024-04-15 16:18:14 -0700
commiteaae766a20fdd2d5f0c6b3f04d7f238a6aa1f814 (patch)
treeb4cd2c8dda9b9094df22c048e3363952874157c5 /compiler-rt
parentc24b41d71f2e5658b0b6618482831f34820f6b4a (diff)
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[RISCV] Support rv{32, 64}e in the compiler builtins (#88252)
Register spills (save/restore) in RISC-V embedded work differently because there are less registers and different stack alignment. [GCC equivalent ](https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/riscv/save-restore.S#L298C16-L336) Follow up from #76777. --------- Signed-off-by: xermicus <cyrill@parity.io> (cherry picked from commit bd32aaa8c9ec2094f605315b3989adc2a567ca98)
Diffstat (limited to 'compiler-rt')
-rw-r--r--compiler-rt/lib/builtins/riscv/restore.S42
-rw-r--r--compiler-rt/lib/builtins/riscv/save.S42
2 files changed, 84 insertions, 0 deletions
diff --git a/compiler-rt/lib/builtins/riscv/restore.S b/compiler-rt/lib/builtins/riscv/restore.S
index 73f64a9..6f43842 100644
--- a/compiler-rt/lib/builtins/riscv/restore.S
+++ b/compiler-rt/lib/builtins/riscv/restore.S
@@ -22,6 +22,8 @@
#if __riscv_xlen == 32
+#ifndef __riscv_32e
+
.globl __riscv_restore_12
.type __riscv_restore_12,@function
__riscv_restore_12:
@@ -86,8 +88,29 @@ __riscv_restore_0:
addi sp, sp, 16
ret
+#else
+
+ .globl __riscv_restore_2
+ .type __riscv_restore_2,@function
+ .globl __riscv_restore_1
+ .type __riscv_restore_1,@function
+ .globl __riscv_restore_0
+ .type __riscv_restore_0,@function
+__riscv_restore_2:
+__riscv_restore_1:
+__riscv_restore_0:
+ lw s1, 0(sp)
+ lw s0, 4(sp)
+ lw ra, 8(sp)
+ addi sp, sp, 12
+ ret
+
+#endif
+
#elif __riscv_xlen == 64
+#ifndef __riscv_64e
+
.globl __riscv_restore_12
.type __riscv_restore_12,@function
__riscv_restore_12:
@@ -162,5 +185,24 @@ __riscv_restore_0:
ret
#else
+
+ .globl __riscv_restore_2
+ .type __riscv_restore_2,@function
+ .globl __riscv_restore_1
+ .type __riscv_restore_1,@function
+ .globl __riscv_restore_0
+ .type __riscv_restore_0,@function
+__riscv_restore_2:
+__riscv_restore_1:
+__riscv_restore_0:
+ ld s1, 0(sp)
+ ld s0, 8(sp)
+ ld ra, 16(sp)
+ addi sp, sp, 24
+ ret
+
+#endif
+
+#else
# error "xlen must be 32 or 64 for save-restore implementation
#endif
diff --git a/compiler-rt/lib/builtins/riscv/save.S b/compiler-rt/lib/builtins/riscv/save.S
index 85501ae..3e04417 100644
--- a/compiler-rt/lib/builtins/riscv/save.S
+++ b/compiler-rt/lib/builtins/riscv/save.S
@@ -18,6 +18,8 @@
#if __riscv_xlen == 32
+#ifndef __riscv_32e
+
.globl __riscv_save_12
.type __riscv_save_12,@function
__riscv_save_12:
@@ -92,8 +94,29 @@ __riscv_save_0:
sw ra, 12(sp)
jr t0
+#else
+
+ .globl __riscv_save_2
+ .type __riscv_save_2,@function
+ .globl __riscv_save_1
+ .type __riscv_save_1,@function
+ .globl __riscv_save_0
+ .type __riscv_save_0,@function
+__riscv_save_2:
+__riscv_save_1:
+__riscv_save_0:
+ addi sp, sp, -12
+ sw s1, 0(sp)
+ sw s0, 4(sp)
+ sw ra, 8(sp)
+ jr t0
+
+#endif
+
#elif __riscv_xlen == 64
+#ifndef __riscv_64e
+
.globl __riscv_save_12
.type __riscv_save_12,@function
__riscv_save_12:
@@ -182,5 +205,24 @@ __riscv_save_0:
jr t0
#else
+
+ .globl __riscv_save_2
+ .type __riscv_save_2,@function
+ .globl __riscv_save_1
+ .type __riscv_save_1,@function
+ .globl __riscv_save_0
+ .type __riscv_save_0,@function
+__riscv_save_2:
+__riscv_save_1:
+__riscv_save_0:
+ addi sp, sp, -24
+ sd s1, 0(sp)
+ sd s0, 8(sp)
+ sd ra, 16(sp)
+ jr t0
+
+#endif
+
+#else
# error "xlen must be 32 or 64 for save-restore implementation
#endif