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authorAlex Bradbury <asb@igalia.com>2023-11-29 14:47:36 +0000
committerAlex Bradbury <asb@igalia.com>2023-11-29 14:51:27 +0000
commit738c3ede315acb413fc8e0e15c78657102110e94 (patch)
tree30effb317363a4dbd52631521d5ae0598e8e464f
parent9b192596ded4982ea360e70f723f9d05dc456ec0 (diff)
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[RISCV] Pre-commit test for FrameIndex handling in getMemOperandsWithOffsetWidth
Currently AArch64 handles a FrameIndex operand in this function, but we fail to.
-rw-r--r--llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 43e98d7..135d7db 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -153,6 +153,19 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
.addImm(16);
Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
OffsetIsScalable, Width, TRI);
+
+ // TODO: AArch64 can handle this case, and we probably should too.
+ BaseOps.clear();
+ MMO = MF->getMachineMemOperand(MachinePointerInfo(),
+ MachineMemOperand::MOStore, 4, Align(4));
+ MI = BuildMI(*MF, DL, TII->get(RISCV::SW))
+ .addReg(RISCV::X3)
+ .addFrameIndex(2)
+ .addImm(4)
+ .addMemOperand(MMO);
+ Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
+ OffsetIsScalable, Width, TRI);
+ EXPECT_FALSE(Res);
}
} // namespace