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| author | Alexey Bataev <a.bataev@outlook.com> | 2023-12-20 06:01:59 -0800 |
|---|---|---|
| committer | Alexey Bataev <a.bataev@outlook.com> | 2023-12-20 06:51:39 -0800 |
| commit | a13148a8808d1cc50c97cb2c1411694840a5ddc7 (patch) | |
| tree | 950e693896ee3a1fb5d48f45610ff38024c01771 | |
| parent | 7767c5856d85cd1acf2efc32f77fdf07f00f9ff4 (diff) | |
| download | llvm-a13148a8808d1cc50c97cb2c1411694840a5ddc7.zip llvm-a13148a8808d1cc50c97cb2c1411694840a5ddc7.tar.gz llvm-a13148a8808d1cc50c97cb2c1411694840a5ddc7.tar.bz2 | |
[SLP]Fix PR75995: drop wrapping flags for resized wrapped binops.
If decided to resize the instruction, need to drop wrapping flags from
the resulting vector instructions to avoid incorrect
optimizations/assumptions later.
Fixes PR75995.
| -rw-r--r-- | llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index ee92e10..5c325ad 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -11472,7 +11472,7 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { Value *V = Builder.CreateBinOp( static_cast<Instruction::BinaryOps>(E->getOpcode()), LHS, RHS); - propagateIRFlags(V, E->Scalars, VL0); + propagateIRFlags(V, E->Scalars, VL0, !MinBWs.contains(E)); if (auto *I = dyn_cast<Instruction>(V)) V = propagateMetadata(I, E->Scalars); diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll index 853cf3d..44738aa 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll @@ -11,7 +11,7 @@ define i32 @test() { ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i8> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP2]], <4 x i8> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 6, i32 7> ; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i16> -; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw <4 x i16> [[TMP5]], <i16 -1, i16 0, i16 0, i16 0> +; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i16> [[TMP5]], <i16 -1, i16 0, i16 0, i16 0> ; CHECK-NEXT: [[TMP7:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = zext i16 [[TMP7]] to i32 ; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 65535 |