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author | Wang Pengcheng <wangpengcheng.pp@bytedance.com> | 2024-03-05 10:45:13 +0800 |
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committer | GitHub <noreply@github.com> | 2024-03-05 10:45:13 +0800 |
commit | 0fbe45bdb909ee4c1a928cc1da030f8b09860431 (patch) | |
tree | 9bf9afbebc1d191fe4656dce1e8c9792653becad | |
parent | 65a8e3a400f23eaa1270a5a000e262df954a4ef6 (diff) | |
download | llvm-0fbe45bdb909ee4c1a928cc1da030f8b09860431.zip llvm-0fbe45bdb909ee4c1a928cc1da030f8b09860431.tar.gz llvm-0fbe45bdb909ee4c1a928cc1da030f8b09860431.tar.bz2 |
[RISCV] Add support of Sscofpmf (#83831)
This is used in profile, but somehow we missed it.
-rw-r--r-- | clang/test/Preprocessor/riscv-target-features.c | 9 | ||||
-rw-r--r-- | llvm/docs/RISCVUsage.rst | 3 | ||||
-rw-r--r-- | llvm/lib/Support/RISCVISAInfo.cpp | 1 | ||||
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 3 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/attributes.ll | 4 | ||||
-rw-r--r-- | llvm/test/MC/RISCV/attribute-arch.s | 3 | ||||
-rw-r--r-- | llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 |
7 files changed, 23 insertions, 1 deletions
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 664279c..1a15be1 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -29,6 +29,7 @@ // CHECK-NOT: __riscv_smepmp {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} // CHECK-NOT: __riscv_ssccptr {{.*$}} +// CHECK-NOT: __riscv_sscofpmf {{.*$}} // CHECK-NOT: __riscv_sscounterenw {{.*$}} // CHECK-NOT: __riscv_ssstateen {{.*$}} // CHECK-NOT: __riscv_ssstrict {{.*$}} @@ -352,6 +353,14 @@ // CHECK-SSCCPTR-EXT: __riscv_ssccptr 1000000{{$}} // RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isscofpmf -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCOFPMF-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isscofpmf -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCOFPMF-EXT %s +// CHECK-SSCOFPMF-EXT: __riscv_sscofpmf 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32isscounterenw -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SSCOUNTERENW-EXT %s // RUN: %clang --target=riscv64-unknown-linux-gnu \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 8d293b0..2595af59 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -101,6 +101,7 @@ on support follow. ``Smepmp`` Supported ``Ssaia`` Supported ``Ssccptr`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Sscofpmf`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) @@ -234,7 +235,7 @@ Supported .. _riscv-profiles-extensions-note: -``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` +``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscofpmf``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__. They do not introduce any new features themselves, but instead describe existing hardware features. .. _riscv-zacas-note: diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 68f5c36..54b4dcb 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -65,6 +65,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"smepmp", {1, 0}}, {"ssaia", {1, 0}}, {"ssccptr", {1, 0}}, + {"sscofpmf", {1, 0}}, {"sscounterenw", {1, 0}}, {"ssstateen", {1, 0}}, {"ssstrict", {1, 0}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 9773b29..78f3a82 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -807,6 +807,9 @@ def FeatureStdExtSsccptr : SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", "'Ssccptr' (Main memory supports page table reads)", []>; +def FeatureStdExtSscofpmf + : SubtargetFeature<"sscofpmf", "HasStdExtSscofpmf", "true", + "'Sscofpmf' (Count Overflow and Mode-Based Filtering)", []>; def FeatureStdExtShcounterenw : SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", "'Shcounterenw' (Support writeable hcounteren enable " diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 561b0f2..cc332df 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -42,6 +42,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHGATPA %s ; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSATPA %s ; RUN: llc -mtriple=riscv32 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCPTR %s +; RUN: llc -mtriple=riscv32 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOFPMF %s ; RUN: llc -mtriple=riscv32 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOUNTERENW %s ; RUN: llc -mtriple=riscv32 -mattr=+ssstateen %s -o - | FileCheck --check-prefixes=CHECK,RV32SSSTATEEN %s ; RUN: llc -mtriple=riscv32 -mattr=+ssstrict %s -o - | FileCheck --check-prefixes=CHECK,RV32SSSTRICT %s @@ -166,6 +167,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHGATPA %s ; RUN: llc -mtriple=riscv64 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSATPA %s ; RUN: llc -mtriple=riscv64 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCPTR %s +; RUN: llc -mtriple=riscv64 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOFPMF %s ; RUN: llc -mtriple=riscv64 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOUNTERENW %s ; RUN: llc -mtriple=riscv64 -mattr=+ssstateen %s -o - | FileCheck --check-prefixes=CHECK,RV64SSSTATEEN %s ; RUN: llc -mtriple=riscv64 -mattr=+ssstrict %s -o - | FileCheck --check-prefixes=CHECK,RV64SSSTRICT %s @@ -295,6 +297,7 @@ ; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0" ; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0" ; RV32SSCCPTR: .attribute 5, "rv32i2p1_ssccptr1p0" +; RV32SSCOFPMF: .attribute 5, "rv32i2p1_sscofpmf1p0" ; RV32SSCOUNTERENW: .attribute 5, "rv32i2p1_sscounterenw1p0" ; RV32SSSTATEEN: .attribute 5, "rv32i2p1_ssstateen1p0" ; RV32SSSTRICT: .attribute 5, "rv32i2p1_ssstrict1p0" @@ -421,6 +424,7 @@ ; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0" ; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0" ; RV64SSCCPTR: .attribute 5, "rv64i2p1_ssccptr1p0" +; RV64SSCOFPMF: .attribute 5, "rv64i2p1_sscofpmf1p0" ; RV64SSCOUNTERENW: .attribute 5, "rv64i2p1_sscounterenw1p0" ; RV64SSSTATEEN: .attribute 5, "rv64i2p1_ssstateen1p0" ; RV64SSSTRICT: .attribute 5, "rv64i2p1_ssstrict1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 368d8da..09daeee 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -318,6 +318,9 @@ .attribute arch, "rv32i_ssccptr1p0" # CHECK: attribute 5, "rv32i2p1_ssccptr1p0" +.attribute arch, "rv32i_sscofpmf1p0" +# CHECK: attribute 5, "rv32i2p1_sscofpmf1p0" + .attribute arch, "rv32i_sscounterenw1p0" # CHECK: attribute 5, "rv32i2p1_sscounterenw1p0" diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 82cce23..8a627ec 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -830,6 +830,7 @@ R"(All available -march extensions for RISC-V smepmp 1.0 ssaia 1.0 ssccptr 1.0 + sscofpmf 1.0 sscounterenw 1.0 ssstateen 1.0 ssstrict 1.0 |