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| author | Craig Topper <craig.topper@sifive.com> | 2024-04-19 16:06:25 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2024-04-19 16:06:54 -0700 |
| commit | f09f99ed329f58c79fba43abf5fc73a28a0e2055 (patch) | |
| tree | 7b3e04c77666de03847ba8d653df6fc8f100b3f2 | |
| parent | c69efcd54879835085cf03a09e1eec28dc80e1d3 (diff) | |
| download | llvm-f09f99ed329f58c79fba43abf5fc73a28a0e2055.zip llvm-f09f99ed329f58c79fba43abf5fc73a28a0e2055.tar.gz llvm-f09f99ed329f58c79fba43abf5fc73a28a0e2055.tar.bz2 | |
[RISCV] Add RISCVTuneProcessorModel to 'generic' CPU. NFC
Remove hardcode GENERIC cpu from RISCVTargetDefEmitter.cpp.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVProcessors.td | 2 | ||||
| -rw-r--r-- | llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index f9a557e..3c86036 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -66,7 +66,7 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", GenericTuneInfo; // Support generic for compatibility with other targets. The triple will be used // to change to the appropriate rv32/rv64 version. -def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo; +def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo; def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32", RocketModel, diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index e57bc6f..62916bd 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -82,7 +82,6 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) { OS << "#ifndef TUNE_PROC\n" << "#define TUNE_PROC(ENUM, NAME)\n" << "#endif\n\n"; - OS << "TUNE_PROC(GENERIC, \"generic\")\n"; for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVTuneProcessorModel")) { |