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author | Vitaly Buka <vitalybuka@google.com> | 2024-03-27 08:45:22 -0700 |
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committer | Vitaly Buka <vitalybuka@google.com> | 2024-03-27 08:45:22 -0700 |
commit | 9386aff1a04de43eaf7f337ba51bd4cc641199c9 (patch) | |
tree | 3b7a59185c1a68e8b0dddd0c0b8e356649e04f12 | |
parent | 4955e85002cf9b580c9125efbaa0f36989027a75 (diff) | |
parent | 577e0ef94fb0b4ba9f97a6f58a1961f7ba247d21 (diff) | |
download | llvm-9386aff1a04de43eaf7f337ba51bd4cc641199c9.zip llvm-9386aff1a04de43eaf7f337ba51bd4cc641199c9.tar.gz llvm-9386aff1a04de43eaf7f337ba51bd4cc641199c9.tar.bz2 |
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
6 files changed, 81 insertions, 28 deletions
diff --git a/clang/unittests/AST/DeclPrinterTest.cpp b/clang/unittests/AST/DeclPrinterTest.cpp index 07fa02b..8a29d05 100644 --- a/clang/unittests/AST/DeclPrinterTest.cpp +++ b/clang/unittests/AST/DeclPrinterTest.cpp @@ -1391,7 +1391,7 @@ TEST(DeclPrinter, TestCXXRecordDecl17) { "struct X {};" "Z<X> A;", "A", "Z<X> A")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; } TEST(DeclPrinter, TestCXXRecordDecl18) { @@ -1402,7 +1402,7 @@ TEST(DeclPrinter, TestCXXRecordDecl18) { "struct Y{};" "Y<Z<X>, 2> B;", "B", "Y<Z<X>, 2> B")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; } TEST(DeclPrinter, TestCXXRecordDecl19) { @@ -1413,7 +1413,7 @@ TEST(DeclPrinter, TestCXXRecordDecl19) { "struct Y{};" "Y<Z<X>, 2> B;", "B", "Y<Z<X>, 2> B")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = true; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = true; }; } TEST(DeclPrinter, TestCXXRecordDecl20) { ASSERT_TRUE(PrintedDeclCXX98Matches( @@ -1432,7 +1432,7 @@ TEST(DeclPrinter, TestCXXRecordDecl20) { "Outer<Inner<int, 10>, 5>::NestedStruct nestedInstance(100);", "nestedInstance", "Outer<Inner<int, 10>, 5>::NestedStruct nestedInstance(100)")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; } TEST(DeclPrinter, TestCXXRecordDecl21) { @@ -1452,7 +1452,7 @@ TEST(DeclPrinter, TestCXXRecordDecl21) { "Outer<Inner<int, 10>, 5>::NestedStruct nestedInstance(100);", "nestedInstance", "Outer<Inner<int, 10>, 5>::NestedStruct nestedInstance(100)")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = true; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = true; }; } TEST(DeclPrinter, TestFunctionParamUglified) { diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index df289be..000d01b 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -1676,3 +1676,17 @@ bool RISCVTTIImpl::isLegalMaskedCompressStore(Type *DataTy, Align Alignment) { return false; return true; } + +bool RISCVTTIImpl::areInlineCompatible(const Function *Caller, + const Function *Callee) const { + const TargetMachine &TM = getTLI()->getTargetMachine(); + + const FeatureBitset &CallerBits = + TM.getSubtargetImpl(*Caller)->getFeatureBits(); + const FeatureBitset &CalleeBits = + TM.getSubtargetImpl(*Callee)->getFeatureBits(); + + // Inline a callee if its target-features are a subset of the callers + // target-features. + return (CallerBits & CalleeBits) == CalleeBits; +} diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 8daf684..ac32aea 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -60,6 +60,9 @@ public: : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} + bool areInlineCompatible(const Function *Caller, + const Function *Callee) const; + /// Return the cost of materializing an immediate for a value operand of /// a store instruction. InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo, diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/globals-access.ll b/llvm/test/Instrumentation/HWAddressSanitizer/globals-access.ll index 8c24de7..c83911f 100644 --- a/llvm/test/Instrumentation/HWAddressSanitizer/globals-access.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/globals-access.ll @@ -1,36 +1,36 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --global-value-regex "x" --version 4 -; RUN: opt < %s -S -passes=hwasan -mtriple=aarch64 -hwasan-globals=0 | FileCheck %s --check-prefixes=NOSTACK +; RUN: opt < %s -S -passes=hwasan -mtriple=aarch64 -hwasan-globals=0 | FileCheck %s --check-prefixes=NOGLOB ; RUN: opt < %s -S -passes=hwasan -mtriple=aarch64 -hwasan-globals=1 | FileCheck %s @x = dso_local global i32 0, align 4 ;. -; NOSTACK: @x = dso_local global i32 0, align 4 +; NOGLOB: @x = dso_local global i32 0, align 4 ;. ; CHECK: @x = alias i32, inttoptr (i64 add (i64 ptrtoint (ptr @x.hwasan to i64), i64 5260204364768739328) to ptr) ;. define dso_local noundef i32 @_Z3tmpv() sanitize_hwaddress { -; NOSTACK-LABEL: define dso_local noundef i32 @_Z3tmpv( -; NOSTACK-SAME: ) #[[ATTR0:[0-9]+]] { -; NOSTACK-NEXT: entry: -; NOSTACK-NEXT: [[TMP12:%.*]] = load i64, ptr @__hwasan_tls, align 8 -; NOSTACK-NEXT: [[TMP1:%.*]] = or i64 [[TMP12]], 4294967295 -; NOSTACK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP1]], 1 -; NOSTACK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr -; NOSTACK-NEXT: [[TMP3:%.*]] = lshr i64 ptrtoint (ptr @x to i64), 56 -; NOSTACK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8 -; NOSTACK-NEXT: [[TMP5:%.*]] = and i64 ptrtoint (ptr @x to i64), 72057594037927935 -; NOSTACK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 4 -; NOSTACK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP2]], i64 [[TMP6]] -; NOSTACK-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1 -; NOSTACK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP4]], [[TMP8]] -; NOSTACK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1:![0-9]+]] -; NOSTACK: 10: -; NOSTACK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP2]], ptr @x, i32 2) -; NOSTACK-NEXT: br label [[TMP11]] -; NOSTACK: 11: -; NOSTACK-NEXT: [[TMP0:%.*]] = load i32, ptr @x, align 4 -; NOSTACK-NEXT: ret i32 [[TMP0]] +; NOGLOB-LABEL: define dso_local noundef i32 @_Z3tmpv( +; NOGLOB-SAME: ) #[[ATTR0:[0-9]+]] { +; NOGLOB-NEXT: entry: +; NOGLOB-NEXT: [[TMP12:%.*]] = load i64, ptr @__hwasan_tls, align 8 +; NOGLOB-NEXT: [[TMP1:%.*]] = or i64 [[TMP12]], 4294967295 +; NOGLOB-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP1]], 1 +; NOGLOB-NEXT: [[TMP2:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; NOGLOB-NEXT: [[TMP3:%.*]] = lshr i64 ptrtoint (ptr @x to i64), 56 +; NOGLOB-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8 +; NOGLOB-NEXT: [[TMP5:%.*]] = and i64 ptrtoint (ptr @x to i64), 72057594037927935 +; NOGLOB-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 4 +; NOGLOB-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP2]], i64 [[TMP6]] +; NOGLOB-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1 +; NOGLOB-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP4]], [[TMP8]] +; NOGLOB-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1:![0-9]+]] +; NOGLOB: 10: +; NOGLOB-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP2]], ptr @x, i32 2) +; NOGLOB-NEXT: br label [[TMP11]] +; NOGLOB: 11: +; NOGLOB-NEXT: [[TMP0:%.*]] = load i32, ptr @x, align 4 +; NOGLOB-NEXT: ret i32 [[TMP0]] ; ; CHECK-LABEL: define dso_local noundef i32 @_Z3tmpv( ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { diff --git a/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll b/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll new file mode 100644 index 0000000..b626a22 --- /dev/null +++ b/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll @@ -0,0 +1,34 @@ +; RUN: opt < %s -mtriple=riscv64-unknown-linux-gnu -S -passes=inline | FileCheck %s +; RUN: opt < %s -mtriple=riscv64-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s +; Check that we only inline when we have compatible target attributes. + +target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" +target triple = "riscv64-unknown-linux-gnu" + +define i32 @foo() #0 { +entry: + %call = call i32 (...) @baz() + ret i32 %call +; CHECK-LABEL: foo +; CHECK: call i32 (...) @baz() +} +declare i32 @baz(...) #0 + +define i32 @bar() #1 { +entry: + %call = call i32 @foo() + ret i32 %call +; CHECK-LABEL: bar +; CHECK: call i32 (...) @baz() +} + +define i32 @qux() #0 { +entry: + %call = call i32 @bar() + ret i32 %call +; CHECK-LABEL: qux +; CHECK: call i32 @bar() +} + +attributes #0 = { "target-cpu"="generic-rv64" "target-features"="+f,+d" } +attributes #1 = { "target-cpu"="generic-rv64" "target-features"="+f,+d,+m,+v" } diff --git a/llvm/test/Transforms/Inline/RISCV/lit.local.cfg b/llvm/test/Transforms/Inline/RISCV/lit.local.cfg new file mode 100644 index 0000000..1735174 --- /dev/null +++ b/llvm/test/Transforms/Inline/RISCV/lit.local.cfg @@ -0,0 +1,2 @@ +if not "RISCV" in config.root.targets: + config.unsupported = True |