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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-04-03 22:14:30 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-04-03 22:27:14 +0100 |
| commit | d53b8291bff4542a9c3e2f1df050deafbe295fff (patch) | |
| tree | e2a98752fdb57be7dcf991c748033ae32af32ba8 | |
| parent | 42cbceb0f0160d67145723613fda325dbd129308 (diff) | |
| download | llvm-d53b8291bff4542a9c3e2f1df050deafbe295fff.zip llvm-d53b8291bff4542a9c3e2f1df050deafbe295fff.tar.gz llvm-d53b8291bff4542a9c3e2f1df050deafbe295fff.tar.bz2 | |
[VectorCombine][X86] shuffle-of-casts.ll - adjust zext nneg tests to improve costs for testing
Improves SSE vs AVX test results for #87510
| -rw-r--r-- | llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll index b922528..f804300 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll @@ -17,31 +17,31 @@ define <16 x i32> @concat_zext_v8i16_v16i32(<8 x i16> %a0, <8 x i16> %a1) { ret <16 x i32> %r } -define <16 x i32> @concat_zext_nneg_v8i8_v16i32(<8 x i8> %a0, <8 x i8> %a1) { -; CHECK-LABEL: @concat_zext_nneg_v8i8_v16i32( -; CHECK-NEXT: [[X0:%.*]] = zext nneg <8 x i8> [[A0:%.*]] to <8 x i32> -; CHECK-NEXT: [[X1:%.*]] = zext nneg <8 x i8> [[A1:%.*]] to <8 x i32> +define <16 x i32> @concat_zext_nneg_v8i16_v16i32(<8 x i16> %a0, <8 x i16> %a1) { +; CHECK-LABEL: @concat_zext_nneg_v8i16_v16i32( +; CHECK-NEXT: [[X0:%.*]] = zext nneg <8 x i16> [[A0:%.*]] to <8 x i32> +; CHECK-NEXT: [[X1:%.*]] = zext nneg <8 x i16> [[A1:%.*]] to <8 x i32> ; CHECK-NEXT: [[R:%.*]] = shufflevector <8 x i32> [[X0]], <8 x i32> [[X1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: ret <16 x i32> [[R]] ; - %x0 = zext nneg <8 x i8> %a0 to <8 x i32> - %x1 = zext nneg <8 x i8> %a1 to <8 x i32> + %x0 = zext nneg <8 x i16> %a0 to <8 x i32> + %x1 = zext nneg <8 x i16> %a1 to <8 x i32> %r = shufflevector <8 x i32> %x0, <8 x i32> %x1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i32> %r } ; TODO - sext + zext nneg -> sext -define <8 x i32> @concat_sext_zext_nneg_v4i8_v8i32(<4 x i8> %a0, <4 x i8> %a1) { -; CHECK-LABEL: @concat_sext_zext_nneg_v4i8_v8i32( -; CHECK-NEXT: [[X0:%.*]] = sext <4 x i8> [[A0:%.*]] to <4 x i32> -; CHECK-NEXT: [[X1:%.*]] = zext nneg <4 x i8> [[A1:%.*]] to <4 x i32> -; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[X0]], <4 x i32> [[X1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> -; CHECK-NEXT: ret <8 x i32> [[R]] +define <16 x i32> @concat_sext_zext_nneg_v8i16_v8i32(<8 x i16> %a0, <8 x i16> %a1) { +; CHECK-LABEL: @concat_sext_zext_nneg_v8i16_v8i32( +; CHECK-NEXT: [[X0:%.*]] = sext <8 x i16> [[A0:%.*]] to <8 x i32> +; CHECK-NEXT: [[X1:%.*]] = zext nneg <8 x i16> [[A1:%.*]] to <8 x i32> +; CHECK-NEXT: [[R:%.*]] = shufflevector <8 x i32> [[X0]], <8 x i32> [[X1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-NEXT: ret <16 x i32> [[R]] ; - %x0 = sext <4 x i8> %a0 to <4 x i32> - %x1 = zext nneg <4 x i8> %a1 to <4 x i32> - %r = shufflevector <4 x i32> %x0, <4 x i32> %x1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> - ret <8 x i32> %r + %x0 = sext <8 x i16> %a0 to <8 x i32> + %x1 = zext nneg <8 x i16> %a1 to <8 x i32> + %r = shufflevector <8 x i32> %x0, <8 x i32> %x1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i32> %r } define <16 x i32> @concat_sext_v8i16_v16i32(<8 x i16> %a0, <8 x i16> %a1) { |