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authorFlorian Hahn <flo@fhahn.com>2024-07-09 13:09:39 +0100
committerFlorian Hahn <flo@fhahn.com>2024-07-09 13:09:40 +0100
commitc16e37867ca838621ff9233f4d1a58207c3e99db (patch)
tree5792a678b4e11c2e1c46ed08eca3feb1bb935e8c
parentc530dadebb2c4f073daac3f0ec61bd41fa7a367d (diff)
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[VPlan] Clarify setting Lane in fixPhi (NFCI).
Split off from https://github.com/llvm/llvm-project/pull/94760, clarify as suggested.
-rw-r--r--llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index b051f9d..d315b63 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -189,10 +189,10 @@ bool VPRecipeBase::mayHaveSideEffects() const {
}
void VPLiveOut::fixPhi(VPlan &Plan, VPTransformState &State) {
- auto Lane = VPLane::getLastLaneForVF(State.VF);
VPValue *ExitValue = getOperand(0);
- if (vputils::isUniformAfterVectorization(ExitValue))
- Lane = VPLane::getFirstLane();
+ auto Lane = vputils::isUniformAfterVectorization(ExitValue)
+ ? VPLane::getFirstLane()
+ : VPLane::getLastLaneForVF(State.VF);
VPBasicBlock *MiddleVPBB =
cast<VPBasicBlock>(Plan.getVectorLoopRegion()->getSingleSuccessor());
BasicBlock *MiddleBB = State.CFG.VPBB2IRBB[MiddleVPBB];