diff options
author | Yingwei Zheng <dtcxzyw2333@gmail.com> | 2024-06-09 03:44:19 +0800 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-06-09 03:44:19 +0800 |
commit | 643e4718af3124964cd0f14036bb6fba49e338f7 (patch) | |
tree | 5c3c4a48b3569b99a63eb197c614a5829588dbfb | |
parent | a43d999d1476c8ab549fb9039dccb03217ee1053 (diff) | |
download | llvm-643e4718af3124964cd0f14036bb6fba49e338f7.zip llvm-643e4718af3124964cd0f14036bb6fba49e338f7.tar.gz llvm-643e4718af3124964cd0f14036bb6fba49e338f7.tar.bz2 |
[RISCV][GISel] Add calling convention support for half (#94110)
This patch adds initial support to the half type on RISC-V.
3 files changed, 520 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp index c18892a..beee940 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp @@ -340,7 +340,7 @@ static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget, // supported yet. if (T->isIntegerTy()) return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2; - if (T->isFloatTy() || T->isDoubleTy()) + if (T->isHalfTy() || T->isFloatTy() || T->isDoubleTy()) return true; if (T->isPointerTy()) return true; @@ -361,7 +361,7 @@ static bool isSupportedReturnType(Type *T, const RISCVSubtarget &Subtarget, // supported yet. if (T->isIntegerTy()) return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2; - if (T->isFloatTy() || T->isDoubleTy()) + if (T->isHalfTy() || T->isFloatTy() || T->isDoubleTy()) return true; if (T->isPointerTy()) return true; diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index da8daa5..a091380 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -849,6 +849,8 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank( } if (RB.getID() == RISCV::FPRBRegBankID) { + if (Ty.getSizeInBits() == 16) + return &RISCV::FPR16RegClass; if (Ty.getSizeInBits() == 32) return &RISCV::FPR32RegClass; if (Ty.getSizeInBits() == 64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll new file mode 100644 index 0000000..0a0828e --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll @@ -0,0 +1,516 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator < %s \ +; RUN: | FileCheck -check-prefix=RV32I %s +; RUN: llc -mtriple=riscv32 -mattr=+f -global-isel -stop-after=irtranslator < %s \ +; RUN: | FileCheck -check-prefix=RV32IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfh -global-isel -stop-after=irtranslator < %s \ +; RUN: | FileCheck -check-prefix=RV32IZFH %s + +define half @callee_half_in_regs(half %x) nounwind { + ; RV32I-LABEL: name: callee_half_in_regs + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32IF-LABEL: name: callee_half_in_regs + ; RV32IF: bb.1 (%ir-block.0): + ; RV32IF-NEXT: liveins: $f10_f + ; RV32IF-NEXT: {{ $}} + ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32) + ; RV32IF-NEXT: PseudoRET implicit $f10_f + ; + ; RV32IZFH-LABEL: name: callee_half_in_regs + ; RV32IZFH: bb.1 (%ir-block.0): + ; RV32IZFH-NEXT: liveins: $f10_h + ; RV32IZFH-NEXT: {{ $}} + ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16) + ; RV32IZFH-NEXT: PseudoRET implicit $f10_h + ret half %x +} + +define half @caller_half_in_regs(half %x) nounwind { + ; RV32I-LABEL: name: caller_half_in_regs + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32IF-LABEL: name: caller_half_in_regs + ; RV32IF: bb.1 (%ir-block.0): + ; RV32IF-NEXT: liveins: $f10_f + ; RV32IF-NEXT: {{ $}} + ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32) + ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit-def $f10_f + ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32) + ; RV32IF-NEXT: PseudoRET implicit $f10_f + ; + ; RV32IZFH-LABEL: name: caller_half_in_regs + ; RV32IZFH: bb.1 (%ir-block.0): + ; RV32IZFH-NEXT: liveins: $f10_h + ; RV32IZFH-NEXT: {{ $}} + ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16) + ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_h, implicit-def $f10_h + ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16) + ; RV32IZFH-NEXT: PseudoRET implicit $f10_h + %y = call half @caller_half_in_regs(half %x) + ret half %y +} + +define half @callee_half_mixed_with_int(i32 %x0, half %x) nounwind { + ; RV32I-LABEL: name: callee_half_mixed_with_int + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32IF-LABEL: name: callee_half_mixed_with_int + ; RV32IF: bb.1 (%ir-block.0): + ; RV32IF-NEXT: liveins: $x10, $f10_f + ; RV32IF-NEXT: {{ $}} + ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32) + ; RV32IF-NEXT: PseudoRET implicit $f10_f + ; + ; RV32IZFH-LABEL: name: callee_half_mixed_with_int + ; RV32IZFH: bb.1 (%ir-block.0): + ; RV32IZFH-NEXT: liveins: $x10, $f10_h + ; RV32IZFH-NEXT: {{ $}} + ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16) + ; RV32IZFH-NEXT: PseudoRET implicit $f10_h + ret half %x +} + +define half @caller_half_mixed_with_int(half %x, i32 %x0) nounwind { + ; RV32I-LABEL: name: caller_half_mixed_with_int + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32I-NEXT: $x11 = COPY [[ANYEXT]](s32) + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) + ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32IF-LABEL: name: caller_half_mixed_with_int + ; RV32IF: bb.1 (%ir-block.0): + ; RV32IF-NEXT: liveins: $x10, $f10_f + ; RV32IF-NEXT: {{ $}} + ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32) + ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $f10_f + ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) + ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32) + ; RV32IF-NEXT: PseudoRET implicit $f10_f + ; + ; RV32IZFH-LABEL: name: caller_half_mixed_with_int + ; RV32IZFH: bb.1 (%ir-block.0): + ; RV32IZFH-NEXT: liveins: $x10, $f10_h + ; RV32IZFH-NEXT: {{ $}} + ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IZFH-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16) + ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_h, implicit-def $f10_h + ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16) + ; RV32IZFH-NEXT: PseudoRET implicit $f10_h + %y = call half @callee_half_mixed_with_int(i32 %x0, half %x) + ret half %y +} + +define half @callee_half_return_stack1(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, i32 %v6, i32 %v7, i32 %v8, half %x) nounwind { + ; RV32I-LABEL: name: callee_half_return_stack1 + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; RV32I-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; RV32I-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32I-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32I-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16) + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32) + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32IF-LABEL: name: callee_half_return_stack1 + ; RV32IF: bb.1 (%ir-block.0): + ; RV32IF-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f + ; RV32IF-NEXT: {{ $}} + ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; RV32IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; RV32IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; RV32IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32IF-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32IF-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32) + ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32) + ; RV32IF-NEXT: PseudoRET implicit $f10_f + ; + ; RV32IZFH-LABEL: name: callee_half_return_stack1 + ; RV32IZFH: bb.1 (%ir-block.0): + ; RV32IZFH-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_h + ; RV32IZFH-NEXT: {{ $}} + ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; RV32IZFH-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; RV32IZFH-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; RV32IZFH-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32IZFH-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32IZFH-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32IZFH-NEXT: [[COPY8:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY8]](s16) + ; RV32IZFH-NEXT: PseudoRET implicit $f10_h + ret half %x +} + +define half @caller_half_return_stack1(i32 %v1, half %x) nounwind { + ; RV32I-LABEL: name: caller_half_return_stack1 + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2 + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C7]](s32) + ; RV32I-NEXT: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16) + ; RV32I-NEXT: $x10 = COPY [[C]](s32) + ; RV32I-NEXT: $x11 = COPY [[C1]](s32) + ; RV32I-NEXT: $x12 = COPY [[C2]](s32) + ; RV32I-NEXT: $x13 = COPY [[COPY]](s32) + ; RV32I-NEXT: $x14 = COPY [[C3]](s32) + ; RV32I-NEXT: $x15 = COPY [[C4]](s32) + ; RV32I-NEXT: $x16 = COPY [[C5]](s32) + ; RV32I-NEXT: $x17 = COPY [[C6]](s32) + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; RV32I-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32) + ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32IF-LABEL: name: caller_half_return_stack1 + ; RV32IF: bb.1 (%ir-block.0): + ; RV32IF-NEXT: liveins: $x10, $f10_f + ; RV32IF-NEXT: {{ $}} + ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32IF-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IF-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IF-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32IF-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; RV32IF-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 + ; RV32IF-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; RV32IF-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: $x10 = COPY [[C]](s32) + ; RV32IF-NEXT: $x11 = COPY [[C1]](s32) + ; RV32IF-NEXT: $x12 = COPY [[C2]](s32) + ; RV32IF-NEXT: $x13 = COPY [[COPY]](s32) + ; RV32IF-NEXT: $x14 = COPY [[C3]](s32) + ; RV32IF-NEXT: $x15 = COPY [[C4]](s32) + ; RV32IF-NEXT: $x16 = COPY [[C5]](s32) + ; RV32IF-NEXT: $x17 = COPY [[C6]](s32) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32) + ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $f10_f + ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) + ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32) + ; RV32IF-NEXT: PseudoRET implicit $f10_f + ; + ; RV32IZFH-LABEL: name: caller_half_return_stack1 + ; RV32IZFH: bb.1 (%ir-block.0): + ; RV32IZFH-NEXT: liveins: $x10, $f10_h + ; RV32IZFH-NEXT: {{ $}} + ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IZFH-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IZFH-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32IZFH-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; RV32IZFH-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 + ; RV32IZFH-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; RV32IZFH-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IZFH-NEXT: $x10 = COPY [[C]](s32) + ; RV32IZFH-NEXT: $x11 = COPY [[C1]](s32) + ; RV32IZFH-NEXT: $x12 = COPY [[C2]](s32) + ; RV32IZFH-NEXT: $x13 = COPY [[COPY]](s32) + ; RV32IZFH-NEXT: $x14 = COPY [[C3]](s32) + ; RV32IZFH-NEXT: $x15 = COPY [[C4]](s32) + ; RV32IZFH-NEXT: $x16 = COPY [[C5]](s32) + ; RV32IZFH-NEXT: $x17 = COPY [[C6]](s32) + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16) + ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_h, implicit-def $f10_h + ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16) + ; RV32IZFH-NEXT: PseudoRET implicit $f10_h + %y = call half @callee_half_return_stack1(i32 0, i32 1, i32 2, i32 %v1, i32 5, i32 6, i32 7, i32 8, half %x) + ret half %y +} + +define half @callee_half_return_stack2(half %v1, half %v2, half %v3, half %v4, half %v5, half %v6, half %v7, half %v8, half %x) nounwind { + ; RV32I-LABEL: name: callee_half_return_stack2 + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; RV32I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; RV32I-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32) + ; RV32I-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; RV32I-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32) + ; RV32I-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 + ; RV32I-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32) + ; RV32I-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 + ; RV32I-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32) + ; RV32I-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 + ; RV32I-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s32) + ; RV32I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16) + ; RV32I-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32) + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC8]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32IF-LABEL: name: callee_half_return_stack2 + ; RV32IF: bb.1 (%ir-block.0): + ; RV32IF-NEXT: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f + ; RV32IF-NEXT: {{ $}} + ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f + ; RV32IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) + ; RV32IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f + ; RV32IF-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32) + ; RV32IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f + ; RV32IF-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32) + ; RV32IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f + ; RV32IF-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32) + ; RV32IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f + ; RV32IF-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32) + ; RV32IF-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f + ; RV32IF-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s32) + ; RV32IF-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IF-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32) + ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC8]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32) + ; RV32IF-NEXT: PseudoRET implicit $f10_f + ; + ; RV32IZFH-LABEL: name: callee_half_return_stack2 + ; RV32IZFH: bb.1 (%ir-block.0): + ; RV32IZFH-NEXT: liveins: $x10, $f10_h, $f11_h, $f12_h, $f13_h, $f14_h, $f15_h, $f16_h, $f17_h + ; RV32IZFH-NEXT: {{ $}} + ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f12_h + ; RV32IZFH-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY $f13_h + ; RV32IZFH-NEXT: [[COPY4:%[0-9]+]]:_(s16) = COPY $f14_h + ; RV32IZFH-NEXT: [[COPY5:%[0-9]+]]:_(s16) = COPY $f15_h + ; RV32IZFH-NEXT: [[COPY6:%[0-9]+]]:_(s16) = COPY $f16_h + ; RV32IZFH-NEXT: [[COPY7:%[0-9]+]]:_(s16) = COPY $f17_h + ; RV32IZFH-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IZFH-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32) + ; RV32IZFH-NEXT: $f10_h = COPY [[TRUNC]](s16) + ; RV32IZFH-NEXT: PseudoRET implicit $f10_h + ret half %x +} + +define half @caller_half_return_stack2(half %x, half %y) nounwind { + ; RV32I-LABEL: name: caller_half_return_stack2 + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200 + ; RV32I-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16) + ; RV32I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16) + ; RV32I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s32) + ; RV32I-NEXT: G_STORE [[ANYEXT8]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; RV32I-NEXT: $x11 = COPY [[ANYEXT1]](s32) + ; RV32I-NEXT: $x12 = COPY [[ANYEXT2]](s32) + ; RV32I-NEXT: $x13 = COPY [[ANYEXT3]](s32) + ; RV32I-NEXT: $x14 = COPY [[ANYEXT4]](s32) + ; RV32I-NEXT: $x15 = COPY [[ANYEXT5]](s32) + ; RV32I-NEXT: $x16 = COPY [[ANYEXT6]](s32) + ; RV32I-NEXT: $x17 = COPY [[ANYEXT7]](s32) + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 + ; RV32I-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32) + ; RV32I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT9]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32IF-LABEL: name: caller_half_return_stack2 + ; RV32IF: bb.1 (%ir-block.0): + ; RV32IF-NEXT: liveins: $f10_f, $f11_f + ; RV32IF-NEXT: {{ $}} + ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; RV32IF-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00 + ; RV32IF-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200 + ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16) + ; RV32IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16) + ; RV32IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32IF-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32IF-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16) + ; RV32IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32) + ; RV32IF-NEXT: $f11_f = COPY [[ANYEXT1]](s32) + ; RV32IF-NEXT: $f12_f = COPY [[ANYEXT2]](s32) + ; RV32IF-NEXT: $f13_f = COPY [[ANYEXT3]](s32) + ; RV32IF-NEXT: $f14_f = COPY [[ANYEXT4]](s32) + ; RV32IF-NEXT: $f15_f = COPY [[ANYEXT5]](s32) + ; RV32IF-NEXT: $f16_f = COPY [[ANYEXT6]](s32) + ; RV32IF-NEXT: $f17_f = COPY [[ANYEXT7]](s32) + ; RV32IF-NEXT: $x10 = COPY [[ANYEXT8]](s32) + ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $f10_f + ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f + ; RV32IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) + ; RV32IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16) + ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT9]](s32) + ; RV32IF-NEXT: PseudoRET implicit $f10_f + ; + ; RV32IZFH-LABEL: name: caller_half_return_stack2 + ; RV32IZFH: bb.1 (%ir-block.0): + ; RV32IZFH-NEXT: liveins: $f10_h, $f11_h + ; RV32IZFH-NEXT: {{ $}} + ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; RV32IZFH-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00 + ; RV32IZFH-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200 + ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16) + ; RV32IZFH-NEXT: $f11_h = COPY [[C]](s16) + ; RV32IZFH-NEXT: $f12_h = COPY [[COPY]](s16) + ; RV32IZFH-NEXT: $f13_h = COPY [[C1]](s16) + ; RV32IZFH-NEXT: $f14_h = COPY [[COPY]](s16) + ; RV32IZFH-NEXT: $f15_h = COPY [[COPY1]](s16) + ; RV32IZFH-NEXT: $f16_h = COPY [[COPY1]](s16) + ; RV32IZFH-NEXT: $f17_h = COPY [[COPY1]](s16) + ; RV32IZFH-NEXT: $x10 = COPY [[COPY]](s16) + ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_h, implicit $f11_h, implicit $f12_h, implicit $f13_h, implicit $f14_h, implicit $f15_h, implicit $f16_h, implicit $f17_h, implicit $x10, implicit-def $f10_h + ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h + ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16) + ; RV32IZFH-NEXT: PseudoRET implicit $f10_h + %z = call half @callee_half_return_stack2(half %x, half 1.0, half %x, half 3.0, half %x, half %y, half %y, half %y, half %x) + ret half %z +} |