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| author | Sergei Barannikov <barannikov88@gmail.com> | 2025-09-01 20:22:53 +0300 |
|---|---|---|
| committer | Sergei Barannikov <barannikov88@gmail.com> | 2025-09-04 19:05:39 +0300 |
| commit | cefa6c8196b1f71010bb8161db53005bea8c9e33 (patch) | |
| tree | 45489ac1c85d6ce1b52863a32ce5301e6612ce57 | |
| parent | 69d0c3e44ff336abaaccc853b5a49b95b87c3cce (diff) | |
| download | llvm-users/s.barannikov/decoder-operands-4-aarch64-tsb.zip llvm-users/s.barannikov/decoder-operands-4-aarch64-tsb.tar.gz llvm-users/s.barannikov/decoder-operands-4-aarch64-tsb.tar.bz2 | |
[AArch64] Correctly disassemble TSB instructionusers/s.barannikov/decoder-operands-4-aarch64-tsb
TSB instruction has one operand, but the generated disassembler didn't
decode this operand. AArch64InstPrinter had a workaround for this.
This instruction can now be disassembled correctly.
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SystemOperands.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/CMakeLists.txt | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 7 |
3 files changed, 2 insertions, 10 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 1b0e90b..65b752e 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -362,7 +362,7 @@ def lookupTSBByName : SearchIndex { let Key = ["Name"]; } -def : TSB<"csync", 0>; +def : TSB<"csync", 2>; //===----------------------------------------------------------------------===// // PRFM (prefetch) instruction options. diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt index 833ce48..79b56ea 100644 --- a/llvm/lib/Target/AArch64/CMakeLists.txt +++ b/llvm/lib/Target/AArch64/CMakeLists.txt @@ -8,8 +8,7 @@ tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1) tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv) tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel) tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler - -ignore-non-decodable-operands - -ignore-fully-defined-operands) + -ignore-non-decodable-operands) tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel) tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel) tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 54b58e9..2552ee3 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -365,13 +365,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, return; } - // Instruction TSB is specified as a one operand instruction, but 'csync' is - // not encoded, so for printing it is treated as a special case here: - if (Opcode == AArch64::TSB) { - O << "\ttsb\tcsync"; - return; - } - if (!PrintAliases || !printAliasInstr(MI, Address, STI, O)) printInstruction(MI, Address, STI, O); |