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author | Brendan Dahl <brendan.dahl@gmail.com> | 2024-05-30 09:02:17 -0700 |
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committer | GitHub <noreply@github.com> | 2024-05-30 09:02:17 -0700 |
commit | 8aa80199751b0cd6631d057b0bfb21584acb206f (patch) | |
tree | 2ce8fa040792808ad6458eb5a6e81211eceb10a6 | |
parent | ed35a92c404650b15a79ff38bcaff41de176cb78 (diff) | |
download | llvm-8aa80199751b0cd6631d057b0bfb21584acb206f.zip llvm-8aa80199751b0cd6631d057b0bfb21584acb206f.tar.gz llvm-8aa80199751b0cd6631d057b0bfb21584acb206f.tar.bz2 |
[WebAssembly] Implement all f16x8 relation instructions. (#93751)
All of these instructions can be generated using regular LL
instructions.
Specified at:
https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md
-rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 11 | ||||
-rw-r--r-- | llvm/test/CodeGen/WebAssembly/half-precision.ll | 54 | ||||
-rw-r--r-- | llvm/test/MC/WebAssembly/simd-encodings.s | 18 |
3 files changed, 81 insertions, 2 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index baf15cc..b800123 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -720,13 +720,19 @@ def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef), // Comparisons //===----------------------------------------------------------------------===// -multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> { +multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop, + list<Predicate> reqs = []> { defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), [(set (vec.int_vt V128:$dst), (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))], vec.prefix#"."#name#"\t$dst, $lhs, $rhs", - vec.prefix#"."#name, simdop>; + vec.prefix#"."#name, simdop, reqs>; +} + +multiclass HalfPrecisionCondition<Vec vec, string name, CondCode cond, + bits<32> simdop> { + defm "" : SIMDCondition<vec, name, cond, simdop, [HasHalfPrecision]>; } multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> { @@ -738,6 +744,7 @@ multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> { multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> { defm "" : SIMDCondition<F32x4, name, cond, baseInst>; defm "" : SIMDCondition<F64x2, name, cond, !add(baseInst, 6)>; + defm "" : HalfPrecisionCondition<F16x8, name, cond, !add(baseInst, 255)>; } // Equality: eq diff --git a/llvm/test/CodeGen/WebAssembly/half-precision.ll b/llvm/test/CodeGen/WebAssembly/half-precision.ll index 73ccea8d..cca25b4 100644 --- a/llvm/test/CodeGen/WebAssembly/half-precision.ll +++ b/llvm/test/CodeGen/WebAssembly/half-precision.ll @@ -103,3 +103,57 @@ define <8 x half> @pmax_intrinsic_v8f16(<8 x half> %a, <8 x half> %b) { %v = call <8 x half> @llvm.wasm.pmax.v8f16(<8 x half> %a, <8 x half> %b) ret <8 x half> %v } + +; CHECK-LABEL: compare_oeq_v8f16: +; CHECK-NEXT: .functype compare_oeq_v8f16 (v128, v128) -> (v128){{$}} +; CHECK-NEXT: f16x8.eq $push[[R:[0-9]+]]=, $0, $1{{$}} +; CHECK-NEXT: return $pop[[R]]{{$}} +define <8 x i1> @compare_oeq_v8f16 (<8 x half> %x, <8 x half> %y) { + %res = fcmp oeq <8 x half> %x, %y + ret <8 x i1> %res +} + +; CHECK-LABEL: compare_une_v8f16: +; CHECK-NEXT: .functype compare_une_v8f16 (v128, v128) -> (v128){{$}} +; CHECK-NEXT: f16x8.ne $push[[R:[0-9]+]]=, $0, $1{{$}} +; CHECK-NEXT: return $pop[[R]]{{$}} +define <8 x i1> @compare_une_v8f16 (<8 x half> %x, <8 x half> %y) { + %res = fcmp une <8 x half> %x, %y + ret <8 x i1> %res +} + +; CHECK-LABEL: compare_olt_v8f16: +; CHECK-NEXT: .functype compare_olt_v8f16 (v128, v128) -> (v128){{$}} +; CHECK-NEXT: f16x8.lt $push[[R:[0-9]+]]=, $0, $1{{$}} +; CHECK-NEXT: return $pop[[R]]{{$}} +define <8 x i1> @compare_olt_v8f16 (<8 x half> %x, <8 x half> %y) { + %res = fcmp olt <8 x half> %x, %y + ret <8 x i1> %res +} + +; CHECK-LABEL: compare_ogt_v8f16: +; CHECK-NEXT: .functype compare_ogt_v8f16 (v128, v128) -> (v128){{$}} +; CHECK-NEXT: f16x8.gt $push[[R:[0-9]+]]=, $0, $1{{$}} +; CHECK-NEXT: return $pop[[R]]{{$}} +define <8 x i1> @compare_ogt_v8f16 (<8 x half> %x, <8 x half> %y) { + %res = fcmp ogt <8 x half> %x, %y + ret <8 x i1> %res +} + +; CHECK-LABEL: compare_ole_v8f16: +; CHECK-NEXT: .functype compare_ole_v8f16 (v128, v128) -> (v128){{$}} +; CHECK-NEXT: f16x8.le $push[[R:[0-9]+]]=, $0, $1{{$}} +; CHECK-NEXT: return $pop[[R]]{{$}} +define <8 x i1> @compare_ole_v8f16 (<8 x half> %x, <8 x half> %y) { + %res = fcmp ole <8 x half> %x, %y + ret <8 x i1> %res +} + +; CHECK-LABEL: compare_oge_v8f16: +; CHECK-NEXT: .functype compare_oge_v8f16 (v128, v128) -> (v128){{$}} +; CHECK-NEXT: f16x8.ge $push[[R:[0-9]+]]=, $0, $1{{$}} +; CHECK-NEXT: return $pop[[R]]{{$}} +define <8 x i1> @compare_oge_v8f16 (<8 x half> %x, <8 x half> %y) { + %res = fcmp oge <8 x half> %x, %y + ret <8 x i1> %res +} diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s index 113a23d..aa70815 100644 --- a/llvm/test/MC/WebAssembly/simd-encodings.s +++ b/llvm/test/MC/WebAssembly/simd-encodings.s @@ -875,4 +875,22 @@ main: # CHECK: f16x8.pmax # encoding: [0xfd,0xbb,0x02] f16x8.pmax + # CHECK: f16x8.eq # encoding: [0xfd,0xc0,0x02] + f16x8.eq + + # CHECK: f16x8.ne # encoding: [0xfd,0xc1,0x02] + f16x8.ne + + # CHECK: f16x8.lt # encoding: [0xfd,0xc2,0x02] + f16x8.lt + + # CHECK: f16x8.gt # encoding: [0xfd,0xc3,0x02] + f16x8.gt + + # CHECK: f16x8.le # encoding: [0xfd,0xc4,0x02] + f16x8.le + + # CHECK: f16x8.ge # encoding: [0xfd,0xc5,0x02] + f16x8.ge + end_function |