diff options
| author | Felix (Ting Wang) <Ting.Wang.SH@ibm.com> | 2024-03-01 08:09:40 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-01 08:09:40 +0800 |
| commit | 5b058709536dd883980722ee000bb7b8c7b2cd8b (patch) | |
| tree | 2b0ba08cb9f8dc133afdbdbfba221f22b97c6b7d | |
| parent | 7d7d4752a8f3d7b83586c10a882f974d821c0c53 (diff) | |
| download | llvm-5b058709536dd883980722ee000bb7b8c7b2cd8b.zip llvm-5b058709536dd883980722ee000bb7b8c7b2cd8b.tar.gz llvm-5b058709536dd883980722ee000bb7b8c7b2cd8b.tar.bz2 | |
[PowerPC] Support local-dynamic TLS relocation on AIX (#66316)
Supports TLS local-dynamic on AIX, generates below sequence of code:
```
.tc foo[TC],foo[TL]@ld # Variable offset, ld relocation specifier
.tc mh[TC],mh[TC]@ml # Module handle for the caller
lwz 3,mh[TC]\(2\) $$ For 64-bit: ld 3,mh[TC]\(2\)
bla .__tls_get_mod # Modifies r0,r3,r4,r5,r11,lr,cr0
#r3 = &TLS for module
lwz 4,foo[TC]\(2\) $$ For 64-bit: ld 4,foo[TC]\(2\)
add 5,3,4 # Compute &foo
.rename mh[TC], "\_$TLSML" # Symbol for the module handle must have the name "_$TLSML"
```
---------
Co-authored-by: tingwang <tingwang@tingwangs-MBP.lan>
Co-authored-by: tingwang <tingwang@tingwangs-MacBook-Pro.local>
26 files changed, 1545 insertions, 521 deletions
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index b13181f..1bc9885 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -693,7 +693,6 @@ def err_drv_cannot_mix_options : Error<"cannot specify '%1' along with '%0'">; def err_drv_invalid_object_mode : Error< "OBJECT_MODE setting %0 is not recognized and is not a valid setting">; -def err_aix_unsupported_tls_model : Error<"TLS model '%0' is not yet supported on AIX">; def err_roptr_requires_data_sections: Error<"-mxcoff-roptr is supported only with -fdata-sections">; def err_roptr_cannot_build_shared: Error<"-mxcoff-roptr is not supported with -shared">; diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 8d7b75b..9555dbf6 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1975,14 +1975,6 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, Opts.LinkBitcodeFiles.push_back(F); } - if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) { - if (T.isOSAIX()) { - StringRef Name = A->getValue(); - if (Name == "local-dynamic") - Diags.Report(diag::err_aix_unsupported_tls_model) << Name; - } - } - if (Arg *A = Args.getLastArg(OPT_fdenormal_fp_math_EQ)) { StringRef Val = A->getValue(); Opts.FPDenormalMode = llvm::parseDenormalFPAttribute(Val); diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index c1c28a7..397b5db 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -2053,12 +2053,6 @@ static void handleTLSModelAttr(Sema &S, Decl *D, const ParsedAttr &AL) { return; } - if (S.Context.getTargetInfo().getTriple().isOSAIX() && - Model == "local-dynamic") { - S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model; - return; - } - D->addAttr(::new (S.Context) TLSModelAttr(S.Context, AL, Model)); } diff --git a/clang/test/CodeGen/PowerPC/aix-tls-model.cpp b/clang/test/CodeGen/PowerPC/aix-tls-model.cpp index 9fdd685..cd0a08a 100644 --- a/clang/test/CodeGen/PowerPC/aix-tls-model.cpp +++ b/clang/test/CodeGen/PowerPC/aix-tls-model.cpp @@ -1,11 +1,11 @@ // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD -// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LD-ERROR +// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LD // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=initial-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-IE // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD -// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s -check-prefix=CHECK-LD-ERROR +// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LD // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=initial-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-IE // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 -ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE @@ -21,7 +21,10 @@ int f() { // CHECK-GD: @z2 ={{.*}} global i32 0 // CHECK-GD: @x ={{.*}} thread_local global i32 0 // CHECK-GD: @_ZZ1fvE1y = internal thread_local global i32 0 -// CHECK-LD-ERROR: error: TLS model 'local-dynamic' is not yet supported on AIX +// CHECK-LD: @z1 ={{.*}} global i32 0 +// CHECK-LD: @z2 ={{.*}} global i32 0 +// CHECK-LD: @x ={{.*}} thread_local(localdynamic) global i32 0 +// CHECK-LD: @_ZZ1fvE1y = internal thread_local(localdynamic) global i32 0 // CHECK-IE: @z1 ={{.*}} global i32 0 // CHECK-IE: @z2 ={{.*}} global i32 0 // CHECK-IE: @x ={{.*}} thread_local(initialexec) global i32 0 diff --git a/clang/test/Sema/aix-attr-tls_model.c b/clang/test/Sema/aix-attr-tls_model.c index 9c22d6c..7c2047b 100644 --- a/clang/test/Sema/aix-attr-tls_model.c +++ b/clang/test/Sema/aix-attr-tls_model.c @@ -6,6 +6,6 @@ #endif static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning -static __thread int y __attribute((tls_model("local-dynamic"))); // expected-error {{TLS model 'local-dynamic' is not yet supported on AIX}} +static __thread int y __attribute((tls_model("local-dynamic"))); // expected-no-diagnostics static __thread int y __attribute((tls_model("initial-exec"))); // no-warning static __thread int y __attribute((tls_model("local-exec"))); // no-warning diff --git a/llvm/include/llvm/MC/MCExpr.h b/llvm/include/llvm/MC/MCExpr.h index b311960..42d2402 100644 --- a/llvm/include/llvm/MC/MCExpr.h +++ b/llvm/include/llvm/MC/MCExpr.h @@ -307,6 +307,8 @@ public: VK_PPC_AIX_TLSGDM, // symbol@m VK_PPC_AIX_TLSIE, // symbol@ie VK_PPC_AIX_TLSLE, // symbol@le + VK_PPC_AIX_TLSLD, // symbol@ld + VK_PPC_AIX_TLSML, // symbol@ml VK_PPC_GOT_TLSLD, // symbol@got@tlsld VK_PPC_GOT_TLSLD_LO, // symbol@got@tlsld@l VK_PPC_GOT_TLSLD_HI, // symbol@got@tlsld@h diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp index 654a615..6943ce2 100644 --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -2418,6 +2418,15 @@ MCSection *TargetLoweringObjectFileXCOFF::getSectionForExternalReference( SmallString<128> Name; getNameWithPrefix(Name, GO, TM); + // AIX TLS local-dynamic does not need the external reference for the + // "_$TLSML" symbol. + if (GO->getThreadLocalMode() == GlobalVariable::LocalDynamicTLSModel && + GO->hasName() && GO->getName() == "_$TLSML") { + return getContext().getXCOFFSection( + Name, SectionKind::getData(), + XCOFF::CsectProperties(XCOFF::XMC_TC, XCOFF::XTY_SD)); + } + XCOFF::StorageMappingClass SMC = isa<Function>(GO) ? XCOFF::XMC_DS : XCOFF::XMC_UA; if (GO->isThreadLocal()) @@ -2675,13 +2684,17 @@ MCSection *TargetLoweringObjectFileXCOFF::getSectionForTOCEntry( // the chance of needing -bbigtoc is decreased. Also, the toc-entry for // EH info is never referenced directly using instructions so it can be // allocated with TE storage-mapping class. + // The "_$TLSML" symbol for TLS local-dynamic mode requires XMC_TC, otherwise + // the AIX assembler will complain. return getContext().getXCOFFSection( cast<MCSymbolXCOFF>(Sym)->getSymbolTableName(), SectionKind::getData(), - XCOFF::CsectProperties((TM.getCodeModel() == CodeModel::Large || - cast<MCSymbolXCOFF>(Sym)->isEHInfo()) - ? XCOFF::XMC_TE - : XCOFF::XMC_TC, - XCOFF::XTY_SD)); + XCOFF::CsectProperties( + ((TM.getCodeModel() == CodeModel::Large && + cast<MCSymbolXCOFF>(Sym)->getSymbolTableName() != "_$TLSML") || + cast<MCSymbolXCOFF>(Sym)->isEHInfo()) + ? XCOFF::XMC_TE + : XCOFF::XMC_TC, + XCOFF::XTY_SD)); } MCSection *TargetLoweringObjectFileXCOFF::getSectionForLSDA( diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp index 485fd18..28b2cbb 100644 --- a/llvm/lib/MC/MCExpr.cpp +++ b/llvm/lib/MC/MCExpr.cpp @@ -338,6 +338,10 @@ StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) { return "ie"; case VK_PPC_AIX_TLSLE: return "le"; + case VK_PPC_AIX_TLSLD: + return "ld"; + case VK_PPC_AIX_TLSML: + return "ml"; case VK_PPC_GOT_TLSLD: return "got@tlsld"; case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l"; case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h"; diff --git a/llvm/lib/MC/XCOFFObjectWriter.cpp b/llvm/lib/MC/XCOFFObjectWriter.cpp index 8809af2..d46bbaf 100644 --- a/llvm/lib/MC/XCOFFObjectWriter.cpp +++ b/llvm/lib/MC/XCOFFObjectWriter.cpp @@ -715,7 +715,8 @@ void XCOFFObjectWriter::recordRelocation(MCAssembler &Asm, if (Type == XCOFF::RelocationType::R_POS || Type == XCOFF::RelocationType::R_TLS || Type == XCOFF::RelocationType::R_TLS_LE || - Type == XCOFF::RelocationType::R_TLS_IE) + Type == XCOFF::RelocationType::R_TLS_IE || + Type == XCOFF::RelocationType::R_TLS_LD) // The FixedValue should be symbol's virtual address in this object file // plus any constant value that we might get. FixedValue = getVirtualAddress(SymA, SymASec) + Target.getConstant(); diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index a804dd8..b849b7b 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -231,12 +231,19 @@ public: MCSymbolXCOFF *TCSym = cast<MCSectionXCOFF>(Streamer.getCurrentSectionOnly()) ->getQualNameSymbol(); - // On AIX, we have a region handle (symbol@m) and the variable offset - // (symbol@{gd|ie|le}) for TLS variables, depending on the TLS model. + // On AIX, we have TLS variable offsets (symbol@({gd|ie|le|ld}) depending + // on the TLS access method (or model). For the general-dynamic access + // method, we also have region handle (symbol@m) for each variable. For + // local-dynamic, there is a module handle (_$TLSML[TC]@ml) for all + // variables. Finally for local-exec and initial-exec, we have a thread + // pointer, in r13 for 64-bit mode and returned by .__get_tpointer for + // 32-bit mode. if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD || Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM || Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE || - Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE) + Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE || + Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLD || + Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSML) OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@" << MCSymbolRefExpr::getVariantKindName(Kind) << '\n'; else diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp index 065daf4..f4998e9 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp @@ -116,6 +116,10 @@ std::pair<uint8_t, uint8_t> PPCXCOFFObjectWriter::getRelocTypeAndSignSize( return {XCOFF::RelocationType::R_TLS_IE, SignAndSizeForFKData}; case MCSymbolRefExpr::VK_PPC_AIX_TLSLE: return {XCOFF::RelocationType::R_TLS_LE, SignAndSizeForFKData}; + case MCSymbolRefExpr::VK_PPC_AIX_TLSLD: + return {XCOFF::RelocationType::R_TLS_LD, SignAndSizeForFKData}; + case MCSymbolRefExpr::VK_PPC_AIX_TLSML: + return {XCOFF::RelocationType::R_TLSML, SignAndSizeForFKData}; case MCSymbolRefExpr::VK_None: return {XCOFF::RelocationType::R_POS, SignAndSizeForFKData}; } diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index 3d9ea56..eb8886d 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -139,6 +139,12 @@ class ModulePass; /// and Local Exec models. MO_TPREL_FLAG, + /// MO_TLSLDM_FLAG - on AIX the ML relocation type is only valid for a + /// reference to a TOC symbol from the symbol itself, and right now its only + /// user is the symbol "_$TLSML". The symbol name is used to decide that + /// the R_TLSML relocation is expected. + MO_TLSLDM_FLAG, + /// MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to /// TLS Local Dynamic model. MO_TLSLD_FLAG, diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 483cd78..9396ca2 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -621,12 +621,23 @@ void PPCAsmPrinter::LowerPATCHPOINT(StackMaps &SM, const MachineInstr &MI) { EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP)); } -/// This helper function creates the TlsGetAddr MCSymbol for AIX. We will -/// create the csect and use the qual-name symbol instead of creating just the -/// external symbol. +/// This helper function creates the TlsGetAddr/TlsGetMod MCSymbol for AIX. We +/// will create the csect and use the qual-name symbol instead of creating just +/// the external symbol. static MCSymbol *createMCSymbolForTlsGetAddr(MCContext &Ctx, unsigned MIOpc) { - StringRef SymName = - MIOpc == PPC::GETtlsTpointer32AIX ? ".__get_tpointer" : ".__tls_get_addr"; + StringRef SymName; + switch (MIOpc) { + default: + SymName = ".__tls_get_addr"; + break; + case PPC::GETtlsTpointer32AIX: + SymName = ".__get_tpointer"; + break; + case PPC::GETtlsMOD32AIX: + case PPC::GETtlsMOD64AIX: + SymName = ".__tls_get_mod"; + break; + } return Ctx .getXCOFFSection(SymName, SectionKind::getText(), XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER)) @@ -668,14 +679,16 @@ void PPCAsmPrinter::EmitTlsCall(const MachineInstr *MI, "GETtls[ld]ADDR[32] must read GPR3"); if (Subtarget->isAIXABI()) { - // On AIX, the variable offset should already be in R4 and the region handle - // should already be in R3. - // For TLSGD, which currently is the only supported access model, we only - // need to generate an absolute branch to .__tls_get_addr. + // For TLSGD, the variable offset should already be in R4 and the region + // handle should already be in R3. We generate an absolute branch to + // .__tls_get_addr. For TLSLD, the module handle should already be in R3. + // We generate an absolute branch to .__tls_get_mod. Register VarOffsetReg = Subtarget->isPPC64() ? PPC::X4 : PPC::R4; (void)VarOffsetReg; - assert(MI->getOperand(2).isReg() && - MI->getOperand(2).getReg() == VarOffsetReg && + assert((MI->getOpcode() == PPC::GETtlsMOD32AIX || + MI->getOpcode() == PPC::GETtlsMOD64AIX || + (MI->getOperand(2).isReg() && + MI->getOperand(2).getReg() == VarOffsetReg)) && "GETtls[ld]ADDR[32] must read GPR4"); EmitAIXTlsCallHelper(MI); return; @@ -844,6 +857,13 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM; if (Flag == PPCII::MO_TLSGD_FLAG || Flag == PPCII::MO_GOT_TLSGD_PCREL_FLAG) return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD; + // For local-dynamic TLS access on AIX, we have one TOC entry for the symbol + // (the variable offset) and one shared TOC entry for the module handle. + // They are differentiated by MO_TLSLD_FLAG and MO_TLSLDM_FLAG. + if (Flag == PPCII::MO_TLSLD_FLAG && IsAIX) + return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLD; + if (Flag == PPCII::MO_TLSLDM_FLAG && IsAIX) + return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSML; return MCSymbolRefExpr::VariantKind::VK_None; }; @@ -1354,6 +1374,11 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { .addExpr(SymGotTlsGD)); return; } + case PPC::GETtlsMOD32AIX: + case PPC::GETtlsMOD64AIX: + // Transform: %r3 = GETtlsMODNNAIX %r3 (for NN == 32/64). + // Into: BLA .__tls_get_mod() + // Input parameter is a module handle (_$TLSML[TC]@ml) for all variables. case PPC::GETtlsADDR: // Transform: %x3 = GETtlsADDR %x3, @sym // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd) @@ -2167,6 +2192,11 @@ void PPCAIXAsmPrinter::emitLinkage(const GlobalValue *GV, } } + // Do not emit the _$TLSML symbol. + if (GV->getThreadLocalMode() == GlobalVariable::LocalDynamicTLSModel && + GV->hasName() && GV->getName() == "_$TLSML") + return; + OutStreamer->emitXCOFFSymbolLinkageWithVisibility(GVSym, LinkageAttr, VisibilityAttr); } @@ -2981,11 +3011,13 @@ void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) { MMI->hasDebugInfo()); break; } + case PPC::GETtlsMOD32AIX: + case PPC::GETtlsMOD64AIX: case PPC::GETtlsTpointer32AIX: case PPC::GETtlsADDR64AIX: case PPC::GETtlsADDR32AIX: { - // A reference to .__tls_get_addr/.__get_tpointer is unknown to the - // assembler so we need to emit an external symbol reference. + // A reference to .__tls_get_mod/.__tls_get_addr/.__get_tpointer is unknown + // to the assembler so we need to emit an external symbol reference. MCSymbol *TlsGetAddr = createMCSymbolForTlsGetAddr(OutContext, MI->getOpcode()); ExtSymSDNodeSymbols.insert(TlsGetAddr); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 19cf1a8..9fa17ba 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1774,9 +1774,11 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA"; case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L"; case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR"; + case PPCISD::GET_TLS_MOD_AIX: return "PPCISD::GET_TLS_MOD_AIX"; case PPCISD::GET_TPOINTER: return "PPCISD::GET_TPOINTER"; case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR"; case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX"; + case PPCISD::TLSLD_AIX: return "PPCISD::TLSLD_AIX"; case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA"; case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L"; case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR"; @@ -3415,13 +3417,36 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op, return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset); } - // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently - // supported models. If Local- or Initial-exec are not possible or specified, - // all GlobalTLSAddress nodes are lowered using the general-dynamic model. - // We need to generate two TOC entries, one for the variable offset, one for - // the region handle. The global address for the TOC entry of the region - // handle is created with the MO_TLSGDM_FLAG flag and the global address - // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG. + if (Model == TLSModel::LocalDynamic) { + // For local-dynamic on AIX, we need to generate one TOC entry for each + // variable offset, and a single module-handle TOC entry for the entire + // file. + + SDValue VariableOffsetTGA = + DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSLD_FLAG); + SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA); + + Module *M = DAG.getMachineFunction().getFunction().getParent(); + GlobalVariable *TLSGV = + dyn_cast_or_null<GlobalVariable>(M->getOrInsertGlobal( + StringRef("_$TLSML"), PointerType::getUnqual(*DAG.getContext()))); + TLSGV->setThreadLocalMode(GlobalVariable::LocalDynamicTLSModel); + assert(TLSGV && "Not able to create GV for _$TLSML."); + SDValue ModuleHandleTGA = + DAG.getTargetGlobalAddress(TLSGV, dl, PtrVT, 0, PPCII::MO_TLSLDM_FLAG); + SDValue ModuleHandleTOC = getTOCEntry(DAG, dl, ModuleHandleTGA); + SDValue ModuleHandle = + DAG.getNode(PPCISD::TLSLD_AIX, dl, PtrVT, ModuleHandleTOC); + + return DAG.getNode(ISD::ADD, dl, PtrVT, ModuleHandle, VariableOffset); + } + + // If Local- or Initial-exec or Local-dynamic is not possible or specified, + // all GlobalTLSAddress nodes are lowered using the general-dynamic model. We + // need to generate two TOC entries, one for the variable offset, one for the + // region handle. The global address for the TOC entry of the region handle is + // created with the MO_TLSGDM_FLAG flag and the global address for the TOC + // entry of the variable offset is created with MO_TLSGD_FLAG. SDValue VariableOffsetTGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG); SDValue RegionHandleTGA = diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 509a22b..0bdfdcd 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -370,11 +370,22 @@ namespace llvm { /// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY /// Op that combines two register copies of TOC entries /// (region handle into R3 and variable offset into R4) followed by a - /// GET_TLS_ADDR node which will be expanded to a call to __get_tls_addr. + /// GET_TLS_ADDR node which will be expanded to a call to .__tls_get_addr. /// This node is used in 64-bit mode as well (in which case the result is /// G8RC and inputs are X3/X4). TLSGD_AIX, + /// %x3 = GET_TLS_MOD_AIX _$TLSML - For the AIX local-dynamic TLS model, + /// produces a call to .__tls_get_mod(_$TLSML\@ml). + GET_TLS_MOD_AIX, + + /// [GP|G8]RC = TLSLD_AIX, TOC_ENTRY(module handle) + /// Op that requires a single input of the module handle TOC entry in R3, + /// and generates a GET_TLS_MOD_AIX node which will be expanded into a call + /// to .__tls_get_mod. This node is used in both 32-bit and 64-bit modes. + /// The only difference is the register class. + TLSLD_AIX, + /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS /// model, produces an ADDIS8 instruction that adds the GOT base /// register to sym\@got\@tlsld\@ha. diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 0322bb3..2949d58 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -1557,12 +1557,19 @@ def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; // so we don't need to mark it with a size of 8 bytes. Finally, the assembly // manual mentions this exact set of registers as the clobbered set, others // are guaranteed not to be clobbered. -let Defs = [X0,X4,X5,X11,LR8,CR0] in +let Defs = [X0,X4,X5,X11,LR8,CR0] in { def GETtlsADDR64AIX : PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), "GETtlsADDR64AIX", [(set i64:$rD, (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; +// On AIX, the call to .__tls_get_mod needs one input in X3 for the module handle. +def GETtlsMOD64AIX : + PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$handle), + "GETtlsMOD64AIX", + [(set i64:$rD, + (PPCgetTlsMod i64:$handle))]>, isPPC64; +} } // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 @@ -1595,6 +1602,9 @@ def TLSGDAIX8 : "#TLSGDAIX8", [(set i64:$rD, (PPCTlsgdAIX i64:$offset, i64:$handle))]>; +// This pseudo is expanded to the call to GETtlsMOD64AIX. +def TLSLDAIX8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$handle), + "#TLSLDAIX8", [(set i64:$rD, (PPCTlsldAIX i64:$handle))]>; // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 // are true defines, while the rest of the Defs are clobbers. let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 68cc76a..1c610b2 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2965,6 +2965,7 @@ PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"}, {MO_TLSGD_FLAG, "ppc-tlsgd"}, {MO_TPREL_FLAG, "ppc-tprel"}, + {MO_TLSLDM_FLAG, "ppc-tlsldm"}, {MO_TLSLD_FLAG, "ppc-tlsld"}, {MO_TLSGDM_FLAG, "ppc-tlsgdm"}, {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"}, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 3abd97f..82da1a3 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -213,12 +213,14 @@ def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; +def PPCgetTlsMod : SDNode<"PPCISD::GET_TLS_MOD_AIX", SDTIntUnaryOp>; def PPCgetTpointer : SDNode<"PPCISD::GET_TPOINTER", SDTIntLeaf, []>; def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", SDTypeProfile<1, 3, [ SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; +def PPCTlsldAIX : SDNode<"PPCISD::TLSLD_AIX", SDTIntUnaryOp>; def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; @@ -3249,11 +3251,16 @@ def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$s // The rest of the Defs are the exact set of registers that will be clobbered by // the call. let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, - Defs = [R0,R4,R5,R11,LR,CR0] in + Defs = [R0,R4,R5,R11,LR,CR0] in { def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), "GETtlsADDR32AIX", [(set i32:$rD, (PPCgetTlsAddr i32:$offset, i32:$handle))]>; +def GETtlsMOD32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle), + "GETtlsMOD32AIX", + [(set i32:$rD, + (PPCgetTlsMod i32:$handle))]>; +} // For local-exec accesses on 32-bit AIX, a call to .__get_tpointer is // generated to retrieve the thread pointer. GETtlsTpointer32AIX clobbers both @@ -3293,6 +3300,9 @@ def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handl "#TLSGDAIX", [(set i32:$rD, (PPCTlsgdAIX i32:$offset, i32:$handle))]>; +// This pseudo is expanded to the call to GETtlsMOD32AIX. +def TLSLDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle), + "#TLSLDAIX", [(set i32:$rD, (PPCTlsldAIX i32:$handle))]>; // LR is a true define, while the rest of the Defs are clobbers. R3 is // explicitly defined when this op is created, so not mentioned here. let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, diff --git a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp index 9518d53..147438d 100644 --- a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp +++ b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp @@ -48,9 +48,15 @@ protected: bool processBlock(MachineBasicBlock &MBB) { bool Changed = false; bool NeedFence = true; - bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64(); - bool IsAIX = MBB.getParent()->getSubtarget<PPCSubtarget>().isAIXABI(); + const PPCSubtarget &Subtarget = + MBB.getParent()->getSubtarget<PPCSubtarget>(); + bool Is64Bit = Subtarget.isPPC64(); + bool IsAIX = Subtarget.isAIXABI(); + bool IsLargeModel = + Subtarget.getTargetMachine().getCodeModel() == CodeModel::Large; bool IsPCREL = false; + MachineFunction *MF = MBB.getParent(); + MachineRegisterInfo &RegInfo = MF->getRegInfo(); for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); I != IE;) { @@ -59,13 +65,16 @@ protected: // There are a number of slight differences in code generation // when we call .__get_tpointer (32-bit AIX TLS). bool IsTLSTPRelMI = MI.getOpcode() == PPC::GETtlsTpointer32AIX; + bool IsTLSLDAIXMI = (MI.getOpcode() == PPC::TLSLDAIX8 || + MI.getOpcode() == PPC::TLSLDAIX); if (MI.getOpcode() != PPC::ADDItlsgdLADDR && MI.getOpcode() != PPC::ADDItlsldLADDR && MI.getOpcode() != PPC::ADDItlsgdLADDR32 && MI.getOpcode() != PPC::ADDItlsldLADDR32 && MI.getOpcode() != PPC::TLSGDAIX && - MI.getOpcode() != PPC::TLSGDAIX8 && !IsTLSTPRelMI && !IsPCREL) { + MI.getOpcode() != PPC::TLSGDAIX8 && !IsTLSTPRelMI && !IsPCREL && + !IsTLSLDAIXMI) { // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP // as scheduling fences, we skip creating fences if we already // have existing ADJCALLSTACKDOWN/UP to avoid nesting, @@ -109,6 +118,16 @@ protected: Opc1 = PPC::ADDItlsldL32; Opc2 = PPC::GETtlsldADDR32; break; + case PPC::TLSLDAIX: + // TLSLDAIX is expanded to one copy and GET_TLS_MOD, so we only set + // Opc2 here. + Opc2 = PPC::GETtlsMOD32AIX; + break; + case PPC::TLSLDAIX8: + // TLSLDAIX8 is expanded to one copy and GET_TLS_MOD, so we only set + // Opc2 here. + Opc2 = PPC::GETtlsMOD64AIX; + break; case PPC::TLSGDAIX8: // TLSGDAIX8 is expanded to two copies and GET_TLS_ADDR, so we only // set Opc2 here. @@ -145,9 +164,97 @@ protected: .addImm(0); if (IsAIX) { - // The variable offset and region handle are copied in r4 and r3. The - // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX. - if (!IsTLSTPRelMI) { + if (IsTLSLDAIXMI) { + // The relative order between the node that loads the variable + // offset from the TOC, and the .__tls_get_mod node is being tuned + // here. It is better to put the variable offset TOC load after the + // call, since this node can use clobbers r4/r5. + // Search for the pattern of the two nodes that load from the TOC + // (either for the variable offset or for the module handle), and + // then move the variable offset TOC load right before the node that + // uses the OutReg of the .__tls_get_mod node. + unsigned LDTocOp = + Is64Bit ? (IsLargeModel ? PPC::LDtocL : PPC::LDtoc) + : (IsLargeModel ? PPC::LWZtocL : PPC::LWZtoc); + if (!RegInfo.use_empty(OutReg)) { + std::set<MachineInstr *> Uses; + // Collect all instructions that use the OutReg. + for (MachineOperand &MO : RegInfo.use_operands(OutReg)) + Uses.insert(MO.getParent()); + // Find the first user (e.g.: lwax/stfdx) of the OutReg within the + // current BB. + MachineBasicBlock::iterator UseIter = MBB.begin(); + for (MachineBasicBlock::iterator IE = MBB.end(); UseIter != IE; + ++UseIter) + if (Uses.count(&*UseIter)) + break; + + // Additional handling is required when UserIter (the first user + // of OutReg) is pointing to a valid node that loads from the TOC. + // Check the pattern and do the movement if the pattern matches. + if (UseIter != MBB.end()) { + // Collect all associated nodes that load from the TOC. Use + // hasOneDef() to guard against unexpected scenarios. + std::set<MachineInstr *> LoadFromTocs; + for (MachineOperand &MO : UseIter->operands()) + if (MO.isReg() && MO.isUse()) { + Register MOReg = MO.getReg(); + if (RegInfo.hasOneDef(MOReg)) { + MachineInstr *Temp = + RegInfo.getOneDef(MOReg)->getParent(); + // For the current TLSLDAIX node, get the corresponding + // node that loads from the TOC for the InReg. Otherwise, + // Temp probably pointed to the variable offset TOC load + // we would like to move. + if (Temp == &MI && RegInfo.hasOneDef(InReg)) + Temp = RegInfo.getOneDef(InReg)->getParent(); + if (Temp->getOpcode() == LDTocOp) + LoadFromTocs.insert(Temp); + } else { + // FIXME: analyze this scenario if there is one. + LoadFromTocs.clear(); + break; + } + } + + // Check the two nodes that loaded from the TOC: one should be + // "_$TLSML", and the other will be moved before the node that + // uses the OutReg of the .__tls_get_mod node. + if (LoadFromTocs.size() == 2) { + MachineBasicBlock::iterator TLSMLIter = MBB.end(); + MachineBasicBlock::iterator OffsetIter = MBB.end(); + // Make sure the two nodes that loaded from the TOC are within + // the current BB, and that one of them is from the "_$TLSML" + // pseudo symbol, while the other is from the variable. + for (MachineBasicBlock::iterator I = MBB.begin(), + IE = MBB.end(); + I != IE; ++I) + if (LoadFromTocs.count(&*I)) { + MachineOperand MO = I->getOperand(1); + if (MO.isGlobal() && MO.getGlobal()->hasName() && + MO.getGlobal()->getName() == "_$TLSML") + TLSMLIter = I; + else + OffsetIter = I; + } + // Perform the movement when the desired scenario has been + // identified, which should be when both of the iterators are + // valid. + if (TLSMLIter != MBB.end() && OffsetIter != MBB.end()) + OffsetIter->moveBefore(&*UseIter); + } + } + } + // The module-handle is copied into r3. The copy is followed by + // GETtlsMOD32AIX/GETtlsMOD64AIX. + BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) + .addReg(InReg); + // The call to .__tls_get_mod. + BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3); + } else if (!IsTLSTPRelMI) { + // The variable offset and region handle (for TLSGD) are copied in + // r4 and r3. The copies are followed by + // GETtlsADDR32AIX/GETtlsADDR64AIX. BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4) .addReg(MI.getOperand(1).getReg()); BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll b/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll index c0ffb81..ae41b6b 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll @@ -156,11 +156,11 @@ define void @storesTIInit(double %Val) #0 { ; SMALL32: # %bb.0: # %entry ; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: stwu 1, -32(1) -; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-tlsgdm) @TIInit -; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit +; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-tlsldm) @"_$TLSML" ; SMALL32-NEXT: stw 0, 40(1) -; SMALL32-NEXT: bla .__tls_get_addr[PR] -; SMALL32-NEXT: stfd 1, 0(3) +; SMALL32-NEXT: bla .__tls_get_mod[PR] +; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsld) @TIInit +; SMALL32-NEXT: stfdx 1, 3, 4 ; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: mtlr 0 @@ -171,12 +171,12 @@ define void @storesTIInit(double %Val) #0 { ; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) -; LARGE32-NEXT: addis 3, L..C4@u(2) -; LARGE32-NEXT: addis 4, L..C5@u(2) -; LARGE32-NEXT: lwz 3, L..C4@l(3) -; LARGE32-NEXT: lwz 4, L..C5@l(4) -; LARGE32-NEXT: bla .__tls_get_addr[PR] -; LARGE32-NEXT: stfd 1, 0(3) +; LARGE32-NEXT: addis 6, L..C4@u(2) +; LARGE32-NEXT: addis 3, L..C5@u(2) +; LARGE32-NEXT: lwz 3, L..C5@l(3) +; LARGE32-NEXT: bla .__tls_get_mod[PR] +; LARGE32-NEXT: lwz 4, L..C4@l(6) +; LARGE32-NEXT: stfdx 1, 3, 4 ; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: mtlr 0 @@ -186,11 +186,11 @@ define void @storesTIInit(double %Val) #0 { ; SMALL64: # %bb.0: # %entry ; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: stdu 1, -48(1) -; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-tlsgdm) @TIInit -; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit +; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-tlsldm) @"_$TLSML" ; SMALL64-NEXT: std 0, 64(1) -; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: stfd 1, 0(3) +; SMALL64-NEXT: bla .__tls_get_mod[PR] +; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsld) @TIInit +; SMALL64-NEXT: stfdx 1, 3, 4 ; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: mtlr 0 @@ -201,12 +201,12 @@ define void @storesTIInit(double %Val) #0 { ; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: addis 3, L..C4@u(2) -; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: std 0, 64(1) +; LARGE64-NEXT: addis 6, L..C5@u(2) ; LARGE64-NEXT: ld 3, L..C4@l(3) -; LARGE64-NEXT: ld 4, L..C5@l(4) -; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: stfd 1, 0(3) +; LARGE64-NEXT: bla .__tls_get_mod[PR] +; LARGE64-NEXT: ld 4, L..C5@l(6) +; LARGE64-NEXT: stfdx 1, 3, 4 ; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: mtlr 0 @@ -452,13 +452,13 @@ define double @loadsTIInit() #1 { ; SMALL32: # %bb.0: # %entry ; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: stwu 1, -32(1) -; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-tlsgdm) @TIInit -; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit +; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-tlsldm) @"_$TLSML" ; SMALL32-NEXT: stw 0, 40(1) -; SMALL32-NEXT: bla .__tls_get_addr[PR] -; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit -; SMALL32-NEXT: lfd 0, 0(3) -; SMALL32-NEXT: lfd 1, 0(4) +; SMALL32-NEXT: bla .__tls_get_mod[PR] +; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsld) @TIInit +; SMALL32-NEXT: lfdx 0, 3, 4 +; SMALL32-NEXT: lwz 3, L..C8(2) # @GInit +; SMALL32-NEXT: lfd 1, 0(3) ; SMALL32-NEXT: fadd 1, 0, 1 ; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: lwz 0, 8(1) @@ -470,12 +470,12 @@ define double @loadsTIInit() #1 { ; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) -; LARGE32-NEXT: addis 3, L..C4@u(2) -; LARGE32-NEXT: addis 4, L..C5@u(2) -; LARGE32-NEXT: lwz 3, L..C4@l(3) -; LARGE32-NEXT: lwz 4, L..C5@l(4) -; LARGE32-NEXT: bla .__tls_get_addr[PR] -; LARGE32-NEXT: lfd 0, 0(3) +; LARGE32-NEXT: addis 6, L..C4@u(2) +; LARGE32-NEXT: addis 3, L..C5@u(2) +; LARGE32-NEXT: lwz 3, L..C5@l(3) +; LARGE32-NEXT: bla .__tls_get_mod[PR] +; LARGE32-NEXT: lwz 4, L..C4@l(6) +; LARGE32-NEXT: lfdx 0, 3, 4 ; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lfd 1, 0(3) @@ -489,13 +489,13 @@ define double @loadsTIInit() #1 { ; SMALL64: # %bb.0: # %entry ; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: stdu 1, -48(1) -; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-tlsgdm) @TIInit -; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit +; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-tlsldm) @"_$TLSML" ; SMALL64-NEXT: std 0, 64(1) -; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: ld 4, L..C8(2) # @GInit -; SMALL64-NEXT: lfd 0, 0(3) -; SMALL64-NEXT: lfd 1, 0(4) +; SMALL64-NEXT: bla .__tls_get_mod[PR] +; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsld) @TIInit +; SMALL64-NEXT: lfdx 0, 3, 4 +; SMALL64-NEXT: ld 3, L..C8(2) # @GInit +; SMALL64-NEXT: lfd 1, 0(3) ; SMALL64-NEXT: fadd 1, 0, 1 ; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: ld 0, 16(1) @@ -507,14 +507,14 @@ define double @loadsTIInit() #1 { ; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: addis 3, L..C4@u(2) -; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: std 0, 64(1) +; LARGE64-NEXT: addis 6, L..C5@u(2) ; LARGE64-NEXT: ld 3, L..C4@l(3) -; LARGE64-NEXT: ld 4, L..C5@l(4) -; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: addis 4, L..C8@u(2) -; LARGE64-NEXT: lfd 0, 0(3) -; LARGE64-NEXT: ld 3, L..C8@l(4) +; LARGE64-NEXT: bla .__tls_get_mod[PR] +; LARGE64-NEXT: ld 4, L..C5@l(6) +; LARGE64-NEXT: addis 5, L..C8@u(2) +; LARGE64-NEXT: lfdx 0, 3, 4 +; LARGE64-NEXT: ld 3, L..C8@l(5) ; LARGE64-NEXT: lfd 1, 0(3) ; LARGE64-NEXT: fadd 1, 0, 1 ; LARGE64-NEXT: addi 1, 1, 48 @@ -610,12 +610,16 @@ entry: ret double %add } -; External symbol reference checks for .__tls_get_addr +; External symbol reference checks for .__tls_get_addr/.__tls_get_mod ; SMALL32: .extern .__tls_get_addr[PR] +; SMALL32: .extern .__tls_get_mod[PR] ; SMALL64: .extern .__tls_get_addr[PR] +; SMALL64: .extern .__tls_get_mod[PR] ; LARGE32: .extern .__tls_get_addr[PR] +; LARGE32: .extern .__tls_get_mod[PR] ; LARGE64: .extern .__tls_get_addr[PR] +; LARGE64: .extern .__tls_get_mod[PR] ; TOC entry checks @@ -629,9 +633,10 @@ entry: ; SMALL32-LABEL: L..C3: ; SMALL32-NEXT: .tc TGInit[TC],TGInit[TL]@gd ; SMALL32-LABEL: L..C4: -; SMALL32-NEXT: .tc .TIInit[TC],TIInit[TL]@m +; SMALL32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; SMALL32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; SMALL32-LABEL: L..C5: -; SMALL32-NEXT: .tc TIInit[TC],TIInit[TL]@gd +; SMALL32-NEXT: .tc TIInit[TC],TIInit[TL]@ld ; SMALL32-LABEL: L..C6: ; SMALL32-NEXT: .tc .TWInit[TC],TWInit[TL]@m ; SMALL32-LABEL: L..C7: @@ -649,9 +654,10 @@ entry: ; LARGE32-LABEL: L..C3: ; LARGE32-NEXT: .tc TGInit[TE],TGInit[TL]@gd ; LARGE32-LABEL: L..C4: -; LARGE32-NEXT: .tc .TIInit[TE],TIInit[TL]@m +; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]@ld ; LARGE32-LABEL: L..C5: -; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]@gd +; LARGE32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; LARGE32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; LARGE32-LABEL: L..C6: ; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m ; LARGE32-LABEL: L..C7: @@ -669,9 +675,10 @@ entry: ; SMALL64-LABEL: L..C3: ; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]@gd ; SMALL64-LABEL: L..C4: -; SMALL64-NEXT: .tc .TIInit[TC],TIInit[TL]@m +; SMALL64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; SMALL64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; SMALL64-LABEL: L..C5: -; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]@gd +; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]@ld ; SMALL64-LABEL: L..C6: ; SMALL64-NEXT: .tc .TWInit[TC],TWInit[TL]@m ; SMALL64-LABEL: L..C7: @@ -689,9 +696,10 @@ entry: ; LARGE64-LABEL: L..C3: ; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]@gd ; LARGE64-LABEL: L..C4: -; LARGE64-NEXT: .tc .TIInit[TE],TIInit[TL]@m +; LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; LARGE64-LABEL: L..C5: -; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]@gd +; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]@ld ; LARGE64-LABEL: L..C6: ; LARGE64-NEXT: .tc .TWInit[TE],TWInit[TL]@m ; LARGE64-LABEL: L..C7: diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll b/llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll index 887c452..bbb8e04 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll @@ -165,10 +165,10 @@ define void @storesTIUninit(i32 %Val) #0 { ; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: mr 6, 3 ; SMALL32-NEXT: lwz 3, L..C4(2) -; SMALL32-NEXT: lwz 4, L..C5(2) ; SMALL32-NEXT: stw 0, 40(1) -; SMALL32-NEXT: bla .__tls_get_addr[PR] -; SMALL32-NEXT: stw 6, 0(3) +; SMALL32-NEXT: bla .__tls_get_mod[PR] +; SMALL32-NEXT: lwz 4, L..C5(2) +; SMALL32-NEXT: stwx 6, 3, 4 ; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: mtlr 0 @@ -180,12 +180,12 @@ define void @storesTIUninit(i32 %Val) #0 { ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) ; LARGE32-NEXT: mr 6, 3 -; LARGE32-NEXT: addis 3, L..C4@u(2) -; LARGE32-NEXT: addis 4, L..C5@u(2) -; LARGE32-NEXT: lwz 3, L..C4@l(3) -; LARGE32-NEXT: lwz 4, L..C5@l(4) -; LARGE32-NEXT: bla .__tls_get_addr[PR] -; LARGE32-NEXT: stw 6, 0(3) +; LARGE32-NEXT: addis 7, L..C4@u(2) +; LARGE32-NEXT: addis 3, L..C5@u(2) +; LARGE32-NEXT: lwz 3, L..C5@l(3) +; LARGE32-NEXT: bla .__tls_get_mod[PR] +; LARGE32-NEXT: lwz 4, L..C4@l(7) +; LARGE32-NEXT: stwx 6, 3, 4 ; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: mtlr 0 @@ -197,10 +197,10 @@ define void @storesTIUninit(i32 %Val) #0 { ; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: ld 3, L..C4(2) -; SMALL64-NEXT: ld 4, L..C5(2) ; SMALL64-NEXT: std 0, 64(1) -; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: stw 6, 0(3) +; SMALL64-NEXT: bla .__tls_get_mod[PR] +; SMALL64-NEXT: ld 4, L..C5(2) +; SMALL64-NEXT: stwx 6, 3, 4 ; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: mtlr 0 @@ -212,12 +212,12 @@ define void @storesTIUninit(i32 %Val) #0 { ; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: addis 3, L..C4@u(2) -; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: std 0, 64(1) +; LARGE64-NEXT: addis 7, L..C5@u(2) ; LARGE64-NEXT: ld 3, L..C4@l(3) -; LARGE64-NEXT: ld 4, L..C5@l(4) -; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: stw 6, 0(3) +; LARGE64-NEXT: bla .__tls_get_mod[PR] +; LARGE64-NEXT: ld 4, L..C5@l(7) +; LARGE64-NEXT: stwx 6, 3, 4 ; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: mtlr 0 @@ -468,11 +468,11 @@ define i32 @loadsTIUninit() #1 { ; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: lwz 3, L..C4(2) -; SMALL32-NEXT: lwz 4, L..C5(2) ; SMALL32-NEXT: stw 0, 40(1) -; SMALL32-NEXT: bla .__tls_get_addr[PR] +; SMALL32-NEXT: bla .__tls_get_mod[PR] +; SMALL32-NEXT: lwz 4, L..C5(2) +; SMALL32-NEXT: lwzx 3, 3, 4 ; SMALL32-NEXT: lwz 4, L..C8(2) -; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 4, 0(4) ; SMALL32-NEXT: add 3, 4, 3 ; SMALL32-NEXT: addi 1, 1, 32 @@ -485,12 +485,12 @@ define i32 @loadsTIUninit() #1 { ; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) -; LARGE32-NEXT: addis 3, L..C4@u(2) -; LARGE32-NEXT: addis 4, L..C5@u(2) -; LARGE32-NEXT: lwz 3, L..C4@l(3) -; LARGE32-NEXT: lwz 4, L..C5@l(4) -; LARGE32-NEXT: bla .__tls_get_addr[PR] -; LARGE32-NEXT: lwz 3, 0(3) +; LARGE32-NEXT: addis 6, L..C4@u(2) +; LARGE32-NEXT: addis 3, L..C5@u(2) +; LARGE32-NEXT: lwz 3, L..C5@l(3) +; LARGE32-NEXT: bla .__tls_get_mod[PR] +; LARGE32-NEXT: lwz 4, L..C4@l(6) +; LARGE32-NEXT: lwzx 3, 3, 4 ; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, 0(4) @@ -505,11 +505,11 @@ define i32 @loadsTIUninit() #1 { ; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: ld 3, L..C4(2) -; SMALL64-NEXT: ld 4, L..C5(2) ; SMALL64-NEXT: std 0, 64(1) -; SMALL64-NEXT: bla .__tls_get_addr[PR] +; SMALL64-NEXT: bla .__tls_get_mod[PR] +; SMALL64-NEXT: ld 4, L..C5(2) +; SMALL64-NEXT: lwzx 3, 3, 4 ; SMALL64-NEXT: ld 4, L..C8(2) -; SMALL64-NEXT: lwz 3, 0(3) ; SMALL64-NEXT: lwz 4, 0(4) ; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: addi 1, 1, 48 @@ -522,14 +522,14 @@ define i32 @loadsTIUninit() #1 { ; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: addis 3, L..C4@u(2) -; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: std 0, 64(1) +; LARGE64-NEXT: addis 6, L..C5@u(2) ; LARGE64-NEXT: ld 3, L..C4@l(3) -; LARGE64-NEXT: ld 4, L..C5@l(4) -; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: addis 4, L..C8@u(2) -; LARGE64-NEXT: lwz 3, 0(3) -; LARGE64-NEXT: ld 4, L..C8@l(4) +; LARGE64-NEXT: bla .__tls_get_mod[PR] +; LARGE64-NEXT: ld 4, L..C5@l(6) +; LARGE64-NEXT: addis 5, L..C8@u(2) +; LARGE64-NEXT: lwzx 3, 3, 4 +; LARGE64-NEXT: ld 4, L..C8@l(5) ; LARGE64-NEXT: lwz 4, 0(4) ; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: addi 1, 1, 48 @@ -625,12 +625,16 @@ entry: ret i32 %add } -; External symbol reference checks for .__tls_get_addr +; External symbol reference checks for .__tls_get_addr/.__tls_get_mod ; SMALL32: .extern .__tls_get_addr[PR] +; SMALL32: .extern .__tls_get_mod[PR] ; SMALL64: .extern .__tls_get_addr[PR] +; SMALL64: .extern .__tls_get_mod[PR] ; LARGE32: .extern .__tls_get_addr[PR] +; LARGE32: .extern .__tls_get_mod[PR] ; LARGE64: .extern .__tls_get_addr[PR] +; LARGE64: .extern .__tls_get_mod[PR] ; TOC entry checks @@ -644,9 +648,10 @@ entry: ; SMALL32-LABEL: L..C3: ; SMALL32-NEXT: .tc TGInit[TC],TGInit[TL]@gd ; SMALL32-LABEL: L..C4: -; SMALL32-NEXT: .tc .TIUninit[TC],TIUninit[UL]@m +; SMALL32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; SMALL32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; SMALL32-LABEL: L..C5: -; SMALL32-NEXT: .tc TIUninit[TC],TIUninit[UL]@gd +; SMALL32-NEXT: .tc TIUninit[TC],TIUninit[UL]@ld ; SMALL32-LABEL: L..C6: ; SMALL32-NEXT: .tc .TWUninit[TC],TWUninit[TL]@m ; SMALL32-LABEL: L..C7: @@ -664,9 +669,10 @@ entry: ; LARGE32-LABEL: L..C3: ; LARGE32-NEXT: .tc TGInit[TE],TGInit[TL]@gd ; LARGE32-LABEL: L..C4: -; LARGE32-NEXT: .tc .TIUninit[TE],TIUninit[UL]@m +; LARGE32-NEXT: .tc TIUninit[TE],TIUninit[UL]@ld ; LARGE32-LABEL: L..C5: -; LARGE32-NEXT: .tc TIUninit[TE],TIUninit[UL]@gd +; LARGE32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; LARGE32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; LARGE32-LABEL: L..C6: ; LARGE32-NEXT: .tc .TWUninit[TE],TWUninit[TL]@m ; LARGE32-LABEL: L..C7: @@ -684,9 +690,10 @@ entry: ; SMALL64-LABEL: L..C3: ; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]@gd ; SMALL64-LABEL: L..C4: -; SMALL64-NEXT: .tc .TIUninit[TC],TIUninit[UL]@m +; SMALL64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; SMALL64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; SMALL64-LABEL: L..C5: -; SMALL64-NEXT: .tc TIUninit[TC],TIUninit[UL]@gd +; SMALL64-NEXT: .tc TIUninit[TC],TIUninit[UL]@ld ; SMALL64-LABEL: L..C6: ; SMALL64-NEXT: .tc .TWUninit[TC],TWUninit[TL]@m ; SMALL64-LABEL: L..C7: @@ -704,9 +711,10 @@ entry: ; LARGE64-LABEL: L..C3: ; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]@gd ; LARGE64-LABEL: L..C4: -; LARGE64-NEXT: .tc .TIUninit[TE],TIUninit[UL]@m +; LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; LARGE64-LABEL: L..C5: -; LARGE64-NEXT: .tc TIUninit[TE],TIUninit[UL]@gd +; LARGE64-NEXT: .tc TIUninit[TE],TIUninit[UL]@ld ; LARGE64-LABEL: L..C6: ; LARGE64-NEXT: .tc .TWUninit[TE],TWUninit[TL]@m ; LARGE64-LABEL: L..C7: diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll b/llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll index 47813b5..ff087a2 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll @@ -97,14 +97,14 @@ define void @storesTIUninit(i64 %Val) #0 { ; SMALL32: # %bb.0: # %entry ; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: stwu 1, -32(1) -; SMALL32-NEXT: mr 6, 4 ; SMALL32-NEXT: mr 7, 3 ; SMALL32-NEXT: lwz 3, L..C2(2) -; SMALL32-NEXT: lwz 4, L..C3(2) ; SMALL32-NEXT: stw 0, 40(1) -; SMALL32-NEXT: bla .__tls_get_addr[PR] +; SMALL32-NEXT: mr 6, 4 +; SMALL32-NEXT: bla .__tls_get_mod[PR] +; SMALL32-NEXT: lwz 4, L..C3(2) +; SMALL32-NEXT: stwux 7, 3, 4 ; SMALL32-NEXT: stw 6, 4(3) -; SMALL32-NEXT: stw 7, 0(3) ; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: mtlr 0 @@ -115,15 +115,15 @@ define void @storesTIUninit(i64 %Val) #0 { ; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) -; LARGE32-NEXT: mr 6, 4 ; LARGE32-NEXT: mr 7, 3 -; LARGE32-NEXT: addis 3, L..C2@u(2) -; LARGE32-NEXT: addis 4, L..C3@u(2) -; LARGE32-NEXT: lwz 3, L..C2@l(3) -; LARGE32-NEXT: lwz 4, L..C3@l(4) -; LARGE32-NEXT: bla .__tls_get_addr[PR] +; LARGE32-NEXT: mr 6, 4 +; LARGE32-NEXT: addis 8, L..C2@u(2) +; LARGE32-NEXT: addis 3, L..C3@u(2) +; LARGE32-NEXT: lwz 3, L..C3@l(3) +; LARGE32-NEXT: bla .__tls_get_mod[PR] +; LARGE32-NEXT: lwz 4, L..C2@l(8) +; LARGE32-NEXT: stwux 7, 3, 4 ; LARGE32-NEXT: stw 6, 4(3) -; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: mtlr 0 @@ -135,10 +135,10 @@ define void @storesTIUninit(i64 %Val) #0 { ; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: ld 3, L..C2(2) -; SMALL64-NEXT: ld 4, L..C3(2) ; SMALL64-NEXT: std 0, 64(1) -; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: std 6, 0(3) +; SMALL64-NEXT: bla .__tls_get_mod[PR] +; SMALL64-NEXT: ld 4, L..C3(2) +; SMALL64-NEXT: stdx 6, 3, 4 ; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: mtlr 0 @@ -150,12 +150,12 @@ define void @storesTIUninit(i64 %Val) #0 { ; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: addis 3, L..C2@u(2) -; LARGE64-NEXT: addis 4, L..C3@u(2) ; LARGE64-NEXT: std 0, 64(1) +; LARGE64-NEXT: addis 7, L..C3@u(2) ; LARGE64-NEXT: ld 3, L..C2@l(3) -; LARGE64-NEXT: ld 4, L..C3@l(4) -; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: std 6, 0(3) +; LARGE64-NEXT: bla .__tls_get_mod[PR] +; LARGE64-NEXT: ld 4, L..C3@l(7) +; LARGE64-NEXT: stdx 6, 3, 4 ; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: mtlr 0 @@ -171,14 +171,14 @@ define void @storesTIInit(i64 %Val) #0 { ; SMALL32: # %bb.0: # %entry ; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: stwu 1, -32(1) -; SMALL32-NEXT: mr 6, 4 ; SMALL32-NEXT: mr 7, 3 -; SMALL32-NEXT: lwz 3, L..C4(2) -; SMALL32-NEXT: lwz 4, L..C5(2) +; SMALL32-NEXT: lwz 3, L..C2(2) ; SMALL32-NEXT: stw 0, 40(1) -; SMALL32-NEXT: bla .__tls_get_addr[PR] +; SMALL32-NEXT: mr 6, 4 +; SMALL32-NEXT: bla .__tls_get_mod[PR] +; SMALL32-NEXT: lwz 4, L..C4(2) +; SMALL32-NEXT: stwux 7, 3, 4 ; SMALL32-NEXT: stw 6, 4(3) -; SMALL32-NEXT: stw 7, 0(3) ; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: mtlr 0 @@ -189,15 +189,15 @@ define void @storesTIInit(i64 %Val) #0 { ; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) -; LARGE32-NEXT: mr 6, 4 ; LARGE32-NEXT: mr 7, 3 -; LARGE32-NEXT: addis 3, L..C4@u(2) -; LARGE32-NEXT: addis 4, L..C5@u(2) -; LARGE32-NEXT: lwz 3, L..C4@l(3) -; LARGE32-NEXT: lwz 4, L..C5@l(4) -; LARGE32-NEXT: bla .__tls_get_addr[PR] +; LARGE32-NEXT: mr 6, 4 +; LARGE32-NEXT: addis 8, L..C4@u(2) +; LARGE32-NEXT: addis 3, L..C3@u(2) +; LARGE32-NEXT: lwz 3, L..C3@l(3) +; LARGE32-NEXT: bla .__tls_get_mod[PR] +; LARGE32-NEXT: lwz 4, L..C4@l(8) +; LARGE32-NEXT: stwux 7, 3, 4 ; LARGE32-NEXT: stw 6, 4(3) -; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: mtlr 0 @@ -208,11 +208,11 @@ define void @storesTIInit(i64 %Val) #0 { ; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: mr 6, 3 -; SMALL64-NEXT: ld 3, L..C4(2) -; SMALL64-NEXT: ld 4, L..C5(2) +; SMALL64-NEXT: ld 3, L..C2(2) ; SMALL64-NEXT: std 0, 64(1) -; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: std 6, 0(3) +; SMALL64-NEXT: bla .__tls_get_mod[PR] +; SMALL64-NEXT: ld 4, L..C4(2) +; SMALL64-NEXT: stdx 6, 3, 4 ; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: mtlr 0 @@ -223,13 +223,13 @@ define void @storesTIInit(i64 %Val) #0 { ; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: mr 6, 3 -; LARGE64-NEXT: addis 3, L..C4@u(2) -; LARGE64-NEXT: addis 4, L..C5@u(2) +; LARGE64-NEXT: addis 3, L..C2@u(2) ; LARGE64-NEXT: std 0, 64(1) -; LARGE64-NEXT: ld 3, L..C4@l(3) -; LARGE64-NEXT: ld 4, L..C5@l(4) -; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: std 6, 0(3) +; LARGE64-NEXT: addis 7, L..C4@u(2) +; LARGE64-NEXT: ld 3, L..C2@l(3) +; LARGE64-NEXT: bla .__tls_get_mod[PR] +; LARGE64-NEXT: ld 4, L..C4@l(7) +; LARGE64-NEXT: stdx 6, 3, 4 ; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: mtlr 0 @@ -247,8 +247,8 @@ define void @storesTWInit(i64 %Val) #0 { ; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: mr 6, 4 ; SMALL32-NEXT: mr 7, 3 -; SMALL32-NEXT: lwz 3, L..C6(2) -; SMALL32-NEXT: lwz 4, L..C7(2) +; SMALL32-NEXT: lwz 3, L..C5(2) +; SMALL32-NEXT: lwz 4, L..C6(2) ; SMALL32-NEXT: stw 0, 40(1) ; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: stw 6, 4(3) @@ -265,10 +265,10 @@ define void @storesTWInit(i64 %Val) #0 { ; LARGE32-NEXT: stw 0, 40(1) ; LARGE32-NEXT: mr 6, 4 ; LARGE32-NEXT: mr 7, 3 -; LARGE32-NEXT: addis 3, L..C6@u(2) -; LARGE32-NEXT: addis 4, L..C7@u(2) -; LARGE32-NEXT: lwz 3, L..C6@l(3) -; LARGE32-NEXT: lwz 4, L..C7@l(4) +; LARGE32-NEXT: addis 3, L..C5@u(2) +; LARGE32-NEXT: addis 4, L..C6@u(2) +; LARGE32-NEXT: lwz 3, L..C5@l(3) +; LARGE32-NEXT: lwz 4, L..C6@l(4) ; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 7, 0(3) @@ -282,8 +282,8 @@ define void @storesTWInit(i64 %Val) #0 { ; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: mr 6, 3 -; SMALL64-NEXT: ld 3, L..C6(2) -; SMALL64-NEXT: ld 4, L..C7(2) +; SMALL64-NEXT: ld 3, L..C5(2) +; SMALL64-NEXT: ld 4, L..C6(2) ; SMALL64-NEXT: std 0, 64(1) ; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: std 6, 0(3) @@ -297,11 +297,11 @@ define void @storesTWInit(i64 %Val) #0 { ; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: mr 6, 3 -; LARGE64-NEXT: addis 3, L..C6@u(2) -; LARGE64-NEXT: addis 4, L..C7@u(2) +; LARGE64-NEXT: addis 3, L..C5@u(2) +; LARGE64-NEXT: addis 4, L..C6@u(2) ; LARGE64-NEXT: std 0, 64(1) -; LARGE64-NEXT: ld 3, L..C6@l(3) -; LARGE64-NEXT: ld 4, L..C7@l(4) +; LARGE64-NEXT: ld 3, L..C5@l(3) +; LARGE64-NEXT: ld 4, L..C6@l(4) ; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: std 6, 0(3) ; LARGE64-NEXT: addi 1, 1, 48 @@ -323,7 +323,7 @@ define i64 @loadsTGInit() #1 { ; SMALL32-NEXT: lwz 4, L..C1(2) ; SMALL32-NEXT: stw 0, 40(1) ; SMALL32-NEXT: bla .__tls_get_addr[PR] -; SMALL32-NEXT: lwz 4, L..C8(2) +; SMALL32-NEXT: lwz 4, L..C7(2) ; SMALL32-NEXT: lwz 5, 4(3) ; SMALL32-NEXT: lwz 6, 4(4) ; SMALL32-NEXT: lwz 3, 0(3) @@ -347,8 +347,8 @@ define i64 @loadsTGInit() #1 { ; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: lwz 4, 4(3) ; LARGE32-NEXT: lwz 3, 0(3) -; LARGE32-NEXT: addis 5, L..C8@u(2) -; LARGE32-NEXT: lwz 5, L..C8@l(5) +; LARGE32-NEXT: addis 5, L..C7@u(2) +; LARGE32-NEXT: lwz 5, L..C7@l(5) ; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: addc 4, 6, 4 @@ -366,7 +366,7 @@ define i64 @loadsTGInit() #1 { ; SMALL64-NEXT: ld 4, L..C1(2) ; SMALL64-NEXT: std 0, 64(1) ; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: ld 4, L..C8(2) +; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 3, 0(3) ; SMALL64-NEXT: ld 4, 0(4) ; SMALL64-NEXT: add 3, 4, 3 @@ -385,9 +385,9 @@ define i64 @loadsTGInit() #1 { ; LARGE64-NEXT: ld 3, L..C0@l(3) ; LARGE64-NEXT: ld 4, L..C1@l(4) ; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: addis 4, L..C8@u(2) +; LARGE64-NEXT: addis 4, L..C7@u(2) ; LARGE64-NEXT: ld 3, 0(3) -; LARGE64-NEXT: ld 4, L..C8@l(4) +; LARGE64-NEXT: ld 4, L..C7@l(4) ; LARGE64-NEXT: ld 4, 0(4) ; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: addi 1, 1, 48 @@ -408,16 +408,16 @@ define i64 @loadsTIUninit() #1 { ; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: lwz 3, L..C2(2) -; SMALL32-NEXT: lwz 4, L..C3(2) ; SMALL32-NEXT: stw 0, 40(1) -; SMALL32-NEXT: bla .__tls_get_addr[PR] -; SMALL32-NEXT: lwz 4, L..C8(2) -; SMALL32-NEXT: lwz 5, 4(3) -; SMALL32-NEXT: lwz 6, 4(4) -; SMALL32-NEXT: lwz 3, 0(3) -; SMALL32-NEXT: lwz 7, 0(4) -; SMALL32-NEXT: addc 4, 6, 5 -; SMALL32-NEXT: adde 3, 7, 3 +; SMALL32-NEXT: bla .__tls_get_mod[PR] +; SMALL32-NEXT: lwz 4, L..C3(2) +; SMALL32-NEXT: lwz 5, L..C7(2) +; SMALL32-NEXT: lwzux 6, 3, 4 +; SMALL32-NEXT: lwz 4, 4(5) +; SMALL32-NEXT: lwz 3, 4(3) +; SMALL32-NEXT: lwz 5, 0(5) +; SMALL32-NEXT: addc 4, 4, 3 +; SMALL32-NEXT: adde 3, 5, 6 ; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: mtlr 0 @@ -428,19 +428,19 @@ define i64 @loadsTIUninit() #1 { ; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) -; LARGE32-NEXT: addis 3, L..C2@u(2) -; LARGE32-NEXT: addis 4, L..C3@u(2) -; LARGE32-NEXT: lwz 3, L..C2@l(3) -; LARGE32-NEXT: lwz 4, L..C3@l(4) -; LARGE32-NEXT: bla .__tls_get_addr[PR] -; LARGE32-NEXT: lwz 4, 4(3) -; LARGE32-NEXT: lwz 3, 0(3) -; LARGE32-NEXT: addis 5, L..C8@u(2) -; LARGE32-NEXT: lwz 5, L..C8@l(5) -; LARGE32-NEXT: lwz 6, 4(5) -; LARGE32-NEXT: lwz 5, 0(5) -; LARGE32-NEXT: addc 4, 6, 4 -; LARGE32-NEXT: adde 3, 5, 3 +; LARGE32-NEXT: addis 6, L..C2@u(2) +; LARGE32-NEXT: addis 3, L..C3@u(2) +; LARGE32-NEXT: lwz 3, L..C3@l(3) +; LARGE32-NEXT: bla .__tls_get_mod[PR] +; LARGE32-NEXT: lwz 4, L..C2@l(6) +; LARGE32-NEXT: lwzux 5, 3, 4 +; LARGE32-NEXT: lwz 3, 4(3) +; LARGE32-NEXT: addis 4, L..C7@u(2) +; LARGE32-NEXT: lwz 4, L..C7@l(4) +; LARGE32-NEXT: lwz 6, 4(4) +; LARGE32-NEXT: lwz 7, 0(4) +; LARGE32-NEXT: addc 4, 6, 3 +; LARGE32-NEXT: adde 3, 7, 5 ; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: mtlr 0 @@ -451,11 +451,11 @@ define i64 @loadsTIUninit() #1 { ; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: ld 3, L..C2(2) -; SMALL64-NEXT: ld 4, L..C3(2) ; SMALL64-NEXT: std 0, 64(1) -; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: ld 4, L..C8(2) -; SMALL64-NEXT: ld 3, 0(3) +; SMALL64-NEXT: bla .__tls_get_mod[PR] +; SMALL64-NEXT: ld 4, L..C3(2) +; SMALL64-NEXT: ldx 3, 3, 4 +; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 4, 0(4) ; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: addi 1, 1, 48 @@ -468,14 +468,14 @@ define i64 @loadsTIUninit() #1 { ; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: addis 3, L..C2@u(2) -; LARGE64-NEXT: addis 4, L..C3@u(2) ; LARGE64-NEXT: std 0, 64(1) +; LARGE64-NEXT: addis 6, L..C3@u(2) ; LARGE64-NEXT: ld 3, L..C2@l(3) -; LARGE64-NEXT: ld 4, L..C3@l(4) -; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: addis 4, L..C8@u(2) -; LARGE64-NEXT: ld 3, 0(3) -; LARGE64-NEXT: ld 4, L..C8@l(4) +; LARGE64-NEXT: bla .__tls_get_mod[PR] +; LARGE64-NEXT: ld 4, L..C3@l(6) +; LARGE64-NEXT: addis 5, L..C7@u(2) +; LARGE64-NEXT: ldx 3, 3, 4 +; LARGE64-NEXT: ld 4, L..C7@l(5) ; LARGE64-NEXT: ld 4, 0(4) ; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: addi 1, 1, 48 @@ -495,17 +495,17 @@ define i64 @loadsTIInit() #1 { ; SMALL32: # %bb.0: # %entry ; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: stwu 1, -32(1) -; SMALL32-NEXT: lwz 3, L..C4(2) -; SMALL32-NEXT: lwz 4, L..C5(2) +; SMALL32-NEXT: lwz 3, L..C2(2) ; SMALL32-NEXT: stw 0, 40(1) -; SMALL32-NEXT: bla .__tls_get_addr[PR] -; SMALL32-NEXT: lwz 4, L..C8(2) -; SMALL32-NEXT: lwz 5, 4(3) -; SMALL32-NEXT: lwz 6, 4(4) -; SMALL32-NEXT: lwz 3, 0(3) -; SMALL32-NEXT: lwz 7, 0(4) -; SMALL32-NEXT: addc 4, 6, 5 -; SMALL32-NEXT: adde 3, 7, 3 +; SMALL32-NEXT: bla .__tls_get_mod[PR] +; SMALL32-NEXT: lwz 4, L..C4(2) +; SMALL32-NEXT: lwz 5, L..C7(2) +; SMALL32-NEXT: lwzux 6, 3, 4 +; SMALL32-NEXT: lwz 4, 4(5) +; SMALL32-NEXT: lwz 3, 4(3) +; SMALL32-NEXT: lwz 5, 0(5) +; SMALL32-NEXT: addc 4, 4, 3 +; SMALL32-NEXT: adde 3, 5, 6 ; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: mtlr 0 @@ -516,19 +516,19 @@ define i64 @loadsTIInit() #1 { ; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) -; LARGE32-NEXT: addis 3, L..C4@u(2) -; LARGE32-NEXT: addis 4, L..C5@u(2) -; LARGE32-NEXT: lwz 3, L..C4@l(3) -; LARGE32-NEXT: lwz 4, L..C5@l(4) -; LARGE32-NEXT: bla .__tls_get_addr[PR] -; LARGE32-NEXT: lwz 4, 4(3) -; LARGE32-NEXT: lwz 3, 0(3) -; LARGE32-NEXT: addis 5, L..C8@u(2) -; LARGE32-NEXT: lwz 5, L..C8@l(5) -; LARGE32-NEXT: lwz 6, 4(5) -; LARGE32-NEXT: lwz 5, 0(5) -; LARGE32-NEXT: addc 4, 6, 4 -; LARGE32-NEXT: adde 3, 5, 3 +; LARGE32-NEXT: addis 6, L..C4@u(2) +; LARGE32-NEXT: addis 3, L..C3@u(2) +; LARGE32-NEXT: lwz 3, L..C3@l(3) +; LARGE32-NEXT: bla .__tls_get_mod[PR] +; LARGE32-NEXT: lwz 4, L..C4@l(6) +; LARGE32-NEXT: lwzux 5, 3, 4 +; LARGE32-NEXT: lwz 3, 4(3) +; LARGE32-NEXT: addis 4, L..C7@u(2) +; LARGE32-NEXT: lwz 4, L..C7@l(4) +; LARGE32-NEXT: lwz 6, 4(4) +; LARGE32-NEXT: lwz 7, 0(4) +; LARGE32-NEXT: addc 4, 6, 3 +; LARGE32-NEXT: adde 3, 7, 5 ; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: mtlr 0 @@ -538,12 +538,12 @@ define i64 @loadsTIInit() #1 { ; SMALL64: # %bb.0: # %entry ; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: stdu 1, -48(1) -; SMALL64-NEXT: ld 3, L..C4(2) -; SMALL64-NEXT: ld 4, L..C5(2) +; SMALL64-NEXT: ld 3, L..C2(2) ; SMALL64-NEXT: std 0, 64(1) -; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: ld 4, L..C8(2) -; SMALL64-NEXT: ld 3, 0(3) +; SMALL64-NEXT: bla .__tls_get_mod[PR] +; SMALL64-NEXT: ld 4, L..C4(2) +; SMALL64-NEXT: ldx 3, 3, 4 +; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 4, 0(4) ; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: addi 1, 1, 48 @@ -555,15 +555,15 @@ define i64 @loadsTIInit() #1 { ; LARGE64: # %bb.0: # %entry ; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: stdu 1, -48(1) -; LARGE64-NEXT: addis 3, L..C4@u(2) -; LARGE64-NEXT: addis 4, L..C5@u(2) +; LARGE64-NEXT: addis 3, L..C2@u(2) ; LARGE64-NEXT: std 0, 64(1) -; LARGE64-NEXT: ld 3, L..C4@l(3) -; LARGE64-NEXT: ld 4, L..C5@l(4) -; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: addis 4, L..C8@u(2) -; LARGE64-NEXT: ld 3, 0(3) -; LARGE64-NEXT: ld 4, L..C8@l(4) +; LARGE64-NEXT: addis 6, L..C4@u(2) +; LARGE64-NEXT: ld 3, L..C2@l(3) +; LARGE64-NEXT: bla .__tls_get_mod[PR] +; LARGE64-NEXT: ld 4, L..C4@l(6) +; LARGE64-NEXT: addis 5, L..C7@u(2) +; LARGE64-NEXT: ldx 3, 3, 4 +; LARGE64-NEXT: ld 4, L..C7@l(5) ; LARGE64-NEXT: ld 4, 0(4) ; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: addi 1, 1, 48 @@ -583,11 +583,11 @@ define i64 @loadsTWInit() #1 { ; SMALL32: # %bb.0: # %entry ; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: stwu 1, -32(1) -; SMALL32-NEXT: lwz 3, L..C6(2) -; SMALL32-NEXT: lwz 4, L..C7(2) +; SMALL32-NEXT: lwz 3, L..C5(2) +; SMALL32-NEXT: lwz 4, L..C6(2) ; SMALL32-NEXT: stw 0, 40(1) ; SMALL32-NEXT: bla .__tls_get_addr[PR] -; SMALL32-NEXT: lwz 4, L..C8(2) +; SMALL32-NEXT: lwz 4, L..C7(2) ; SMALL32-NEXT: lwz 5, 4(3) ; SMALL32-NEXT: lwz 6, 4(4) ; SMALL32-NEXT: lwz 3, 0(3) @@ -604,15 +604,15 @@ define i64 @loadsTWInit() #1 { ; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stw 0, 40(1) -; LARGE32-NEXT: addis 3, L..C6@u(2) -; LARGE32-NEXT: addis 4, L..C7@u(2) -; LARGE32-NEXT: lwz 3, L..C6@l(3) -; LARGE32-NEXT: lwz 4, L..C7@l(4) +; LARGE32-NEXT: addis 3, L..C5@u(2) +; LARGE32-NEXT: addis 4, L..C6@u(2) +; LARGE32-NEXT: lwz 3, L..C5@l(3) +; LARGE32-NEXT: lwz 4, L..C6@l(4) ; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: lwz 4, 4(3) ; LARGE32-NEXT: lwz 3, 0(3) -; LARGE32-NEXT: addis 5, L..C8@u(2) -; LARGE32-NEXT: lwz 5, L..C8@l(5) +; LARGE32-NEXT: addis 5, L..C7@u(2) +; LARGE32-NEXT: lwz 5, L..C7@l(5) ; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: addc 4, 6, 4 @@ -626,11 +626,11 @@ define i64 @loadsTWInit() #1 { ; SMALL64: # %bb.0: # %entry ; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: stdu 1, -48(1) -; SMALL64-NEXT: ld 3, L..C6(2) -; SMALL64-NEXT: ld 4, L..C7(2) +; SMALL64-NEXT: ld 3, L..C5(2) +; SMALL64-NEXT: ld 4, L..C6(2) ; SMALL64-NEXT: std 0, 64(1) ; SMALL64-NEXT: bla .__tls_get_addr[PR] -; SMALL64-NEXT: ld 4, L..C8(2) +; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 3, 0(3) ; SMALL64-NEXT: ld 4, 0(4) ; SMALL64-NEXT: add 3, 4, 3 @@ -643,15 +643,15 @@ define i64 @loadsTWInit() #1 { ; LARGE64: # %bb.0: # %entry ; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: stdu 1, -48(1) -; LARGE64-NEXT: addis 3, L..C6@u(2) -; LARGE64-NEXT: addis 4, L..C7@u(2) +; LARGE64-NEXT: addis 3, L..C5@u(2) +; LARGE64-NEXT: addis 4, L..C6@u(2) ; LARGE64-NEXT: std 0, 64(1) -; LARGE64-NEXT: ld 3, L..C6@l(3) -; LARGE64-NEXT: ld 4, L..C7@l(4) +; LARGE64-NEXT: ld 3, L..C5@l(3) +; LARGE64-NEXT: ld 4, L..C6@l(4) ; LARGE64-NEXT: bla .__tls_get_addr[PR] -; LARGE64-NEXT: addis 4, L..C8@u(2) +; LARGE64-NEXT: addis 4, L..C7@u(2) ; LARGE64-NEXT: ld 3, 0(3) -; LARGE64-NEXT: ld 4, L..C8@l(4) +; LARGE64-NEXT: ld 4, L..C7@l(4) ; LARGE64-NEXT: ld 4, 0(4) ; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: addi 1, 1, 48 @@ -665,12 +665,16 @@ entry: ret i64 %add } -; External symbol reference checks for .__tls_get_addr +; External symbol reference checks for .__tls_get_addr/.__tls_get_mod ; SMALL32: .extern .__tls_get_addr[PR] +; SMALL32: .extern .__tls_get_mod[PR] ; SMALL64: .extern .__tls_get_addr[PR] +; SMALL64: .extern .__tls_get_mod[PR] ; LARGE32: .extern .__tls_get_addr[PR] +; LARGE32: .extern .__tls_get_mod[PR] ; LARGE64: .extern .__tls_get_addr[PR] +; LARGE64: .extern .__tls_get_mod[PR] ; TOC entry checks @@ -680,18 +684,17 @@ entry: ; SMALL32-LABEL: L..C1: ; SMALL32-NEXT: .tc TGInit[TC],TGInit[TL]@gd ; SMALL32-LABEL: L..C2: -; SMALL32-NEXT: .tc .TIUninit[TC],TIUninit[UL]@m +; SMALL32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; SMALL32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; SMALL32-LABEL: L..C3: -; SMALL32-NEXT: .tc TIUninit[TC],TIUninit[UL]@gd +; SMALL32-NEXT: .tc TIUninit[TC],TIUninit[UL]@ld ; SMALL32-LABEL: L..C4: -; SMALL32-NEXT: .tc .TIInit[TC],TIInit[TL]@m +; SMALL32-NEXT: .tc TIInit[TC],TIInit[TL]@ld ; SMALL32-LABEL: L..C5: -; SMALL32-NEXT: .tc TIInit[TC],TIInit[TL]@gd -; SMALL32-LABEL: L..C6: ; SMALL32-NEXT: .tc .TWInit[TC],TWInit[TL]@m -; SMALL32-LABEL: L..C7: +; SMALL32-LABEL: L..C6: ; SMALL32-NEXT: .tc TWInit[TC],TWInit[TL]@gd -; SMALL32-LABEL: L..C8: +; SMALL32-LABEL: L..C7: ; SMALL32-NEXT: .tc GInit[TC],GInit[RW] ; LARGE32-LABEL: .toc @@ -700,18 +703,17 @@ entry: ; LARGE32-LABEL: L..C1: ; LARGE32-NEXT: .tc TGInit[TE],TGInit[TL]@gd ; LARGE32-LABEL: L..C2: -; LARGE32-NEXT: .tc .TIUninit[TE],TIUninit[UL]@m +; LARGE32-NEXT: .tc TIUninit[TE],TIUninit[UL]@ld ; LARGE32-LABEL: L..C3: -; LARGE32-NEXT: .tc TIUninit[TE],TIUninit[UL]@gd +; LARGE32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; LARGE32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; LARGE32-LABEL: L..C4: -; LARGE32-NEXT: .tc .TIInit[TE],TIInit[TL]@m +; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]@ld ; LARGE32-LABEL: L..C5: -; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]@gd -; LARGE32-LABEL: L..C6: ; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m -; LARGE32-LABEL: L..C7: +; LARGE32-LABEL: L..C6: ; LARGE32-NEXT: .tc TWInit[TE],TWInit[TL]@gd -; LARGE32-LABEL: L..C8: +; LARGE32-LABEL: L..C7: ; LARGE32-NEXT: .tc GInit[TE],GInit[RW] ; SMALL64-LABEL: .toc @@ -720,18 +722,17 @@ entry: ; SMALL64-LABEL: L..C1: ; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]@gd ; SMALL64-LABEL: L..C2: -; SMALL64-NEXT: .tc .TIUninit[TC],TIUninit[UL]@m +; SMALL64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; SMALL64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; SMALL64-LABEL: L..C3: -; SMALL64-NEXT: .tc TIUninit[TC],TIUninit[UL]@gd +; SMALL64-NEXT: .tc TIUninit[TC],TIUninit[UL]@ld ; SMALL64-LABEL: L..C4: -; SMALL64-NEXT: .tc .TIInit[TC],TIInit[TL]@m +; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]@ld ; SMALL64-LABEL: L..C5: -; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]@gd -; SMALL64-LABEL: L..C6: ; SMALL64-NEXT: .tc .TWInit[TC],TWInit[TL]@m -; SMALL64-LABEL: L..C7: +; SMALL64-LABEL: L..C6: ; SMALL64-NEXT: .tc TWInit[TC],TWInit[TL]@gd -; SMALL64-LABEL: L..C8: +; SMALL64-LABEL: L..C7: ; SMALL64-NEXT: .tc GInit[TC],GInit[RW] ; LARGE64-LABEL: .toc @@ -740,18 +741,17 @@ entry: ; LARGE64-LABEL: L..C1: ; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]@gd ; LARGE64-LABEL: L..C2: -; LARGE64-NEXT: .tc .TIUninit[TE],TIUninit[UL]@m +; LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" ; LARGE64-LABEL: L..C3: -; LARGE64-NEXT: .tc TIUninit[TE],TIUninit[UL]@gd +; LARGE64-NEXT: .tc TIUninit[TE],TIUninit[UL]@ld ; LARGE64-LABEL: L..C4: -; LARGE64-NEXT: .tc .TIInit[TE],TIInit[TL]@m +; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]@ld ; LARGE64-LABEL: L..C5: -; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]@gd -; LARGE64-LABEL: L..C6: ; LARGE64-NEXT: .tc .TWInit[TE],TWInit[TL]@m -; LARGE64-LABEL: L..C7: +; LARGE64-LABEL: L..C6: ; LARGE64-NEXT: .tc TWInit[TE],TWInit[TL]@gd -; LARGE64-LABEL: L..C8: +; LARGE64-LABEL: L..C7: ; LARGE64-NEXT: .tc GInit[TE],GInit[RW] attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-spe,-vsx" } diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-ld-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-ld-xcoff-reloc-large.ll new file mode 100644 index 0000000..73741a2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-tls-ld-xcoff-reloc-large.ll @@ -0,0 +1,349 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s + +@ThreadLocalVarInit = thread_local(localdynamic) global i64 1, align 8 +@IThreadLocalVarUninit = internal thread_local(localdynamic) global i64 0, align 8 +@IThreadLocalVarUninit2 = internal thread_local(localdynamic) global i64 0, align 8 +declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) + +define void @storeITLUninit(i64 noundef %x) { +entry: + %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit) + store i64 %x, ptr %0, align 8 + ret void +} + +define i64 @loadTLInit() { +entry: + %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit) + %1 = load i64, ptr %0, align 8 + ret i64 %1 +} + +define signext i64 @loadTLUninit() { +entry: + %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit) + store i64 1, ptr %0, align 8 + %1 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit2) + %2 = load i64, ptr %1, align 8 + %add = add nsw i64 %2, 1 + ret i64 %add +} + +; RELOC: File: {{.*}}aix-tls-ld-xcoff-reloc-large.ll.tmp.o +; RELOC-NEXT: Format: aix5coff64-rs6000 +; RELOC-NEXT: Arch: powerpc64 +; RELOC-NEXT: AddressSize: 64bit +; RELOC-NEXT: Relocations [ +; RELOC: Virtual Address: 0xE +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+19]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCU (0x30) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x12 +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCU (0x30) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x1A +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+19]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCL (0x31) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x1C +; RELOC-NEXT: Symbol: .__tls_get_mod ([[#NFA+1]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 26 +; RELOC-NEXT: Type: R_RBA (0x18) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x22 +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCL (0x31) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x4A +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+19]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCU (0x30) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x4E +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+23]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCU (0x30) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x56 +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+19]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCL (0x31) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x58 +; RELOC-NEXT: Symbol: .__tls_get_mod ([[#NFA+1]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 26 +; RELOC-NEXT: Type: R_RBA (0x18) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x5E +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+23]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCL (0x31) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x8A +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+19]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCU (0x30) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x8E +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCU (0x30) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x96 +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+19]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCL (0x31) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x98 +; RELOC-NEXT: Symbol: .__tls_get_mod (3) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 26 +; RELOC-NEXT: Type: R_RBA (0x18) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x9E +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCL (0x31) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0xAA +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+25]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCU (0x30) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0xAE +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+25]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCL (0x31) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x110 +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+19]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 64 +; RELOC-NEXT: Type: R_TLSML (0x25) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x118 +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+29]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 64 +; RELOC-NEXT: Type: R_TLS_LD (0x22) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x120 +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+27]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 64 +; RELOC-NEXT: Type: R_TLS_LD (0x22) +; RELOC-NEXT: } +; RELOC: Virtual Address: 0x128 +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+31]]) +; RELOC-NEXT: IsSigned: No +; RELOC-NEXT: FixupBitValue: 0 +; RELOC-NEXT: Length: 64 +; RELOC-NEXT: Type: R_TLS_LD (0x22) +; RELOC-NEXT: } + +; SYM: File: {{.*}}aix-tls-ld-xcoff-reloc-large.ll.tmp.o +; SYM-NEXT: Format: aix5coff64-rs6000 +; SYM-NEXT: Arch: powerpc64 +; SYM-NEXT: AddressSize: 64bit +; SYM-NEXT: Symbols [ +; SYM: Index: [[#NFA+19]] +; SYM-NEXT: Name: _$TLSML +; SYM-NEXT: Value (RelocatableAddress): 0x110 +; SYM-NEXT: Section: .data +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: [[#NFA+20]] +; SYM-NEXT: SectionLen: 8 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 3 +; SYM-NEXT: SymbolType: XTY_SD (0x1) +; SYM-NEXT: StorageMappingClass: XMC_TC (0x3) +; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) +; SYM-NEXT: } +; SYM-NEXT: } +; SYM: Index: [[#NFA+21]] +; SYM-NEXT: Name: IThreadLocalVarUninit +; SYM-NEXT: Value (RelocatableAddress): 0x118 +; SYM-NEXT: Section: .data +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: [[#NFA+22]] +; SYM-NEXT: SectionLen: 8 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 3 +; SYM-NEXT: SymbolType: XTY_SD (0x1) +; SYM-NEXT: StorageMappingClass: XMC_TE (0x16) +; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) +; SYM-NEXT: } +; SYM-NEXT: } +; SYM: Index: [[#NFA+23]] +; SYM-NEXT: Name: ThreadLocalVarInit +; SYM-NEXT: Value (RelocatableAddress): 0x120 +; SYM-NEXT: Section: .data +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: [[#NFA+24]] +; SYM-NEXT: SectionLen: 8 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 3 +; SYM-NEXT: SymbolType: XTY_SD (0x1) +; SYM-NEXT: StorageMappingClass: XMC_TE (0x16) +; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) +; SYM-NEXT: } +; SYM-NEXT: } +; SYM: Index: [[#NFA+25]] +; SYM-NEXT: Name: IThreadLocalVarUninit2 +; SYM-NEXT: Value (RelocatableAddress): 0x128 +; SYM-NEXT: Section: .data +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: [[#NFA+26]] +; SYM-NEXT: SectionLen: 8 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 3 +; SYM-NEXT: SymbolType: XTY_SD (0x1) +; SYM-NEXT: StorageMappingClass: XMC_TE (0x16) +; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) +; SYM-NEXT: } +; SYM-NEXT: } +; SYM: Index: [[#NFA+27]] +; SYM-NEXT: Name: ThreadLocalVarInit +; SYM-NEXT: Value (RelocatableAddress): 0x0 +; SYM-NEXT: Section: .tdata +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_EXT (0x2) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: [[#NFA+28]] +; SYM-NEXT: SectionLen: 8 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 3 +; SYM-NEXT: SymbolType: XTY_SD (0x1) +; SYM-NEXT: StorageMappingClass: XMC_TL (0x14) +; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) +; SYM-NEXT: } +; SYM-NEXT: } +; SYM: Index: [[#NFA+29]] +; SYM-NEXT: Name: IThreadLocalVarUninit +; SYM-NEXT: Value (RelocatableAddress): 0x8 +; SYM-NEXT: Section: .tbss +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: [[#NFA+30]] +; SYM-NEXT: SectionLen: 8 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 3 +; SYM-NEXT: SymbolType: XTY_CM (0x3) +; SYM-NEXT: StorageMappingClass: XMC_UL (0x15) +; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) +; SYM-NEXT: } +; SYM-NEXT: } +; SYM: Index: [[#NFA+31]] +; SYM-NEXT: Name: IThreadLocalVarUninit2 +; SYM-NEXT: Value (RelocatableAddress): 0x10 +; SYM-NEXT: Section: .tbss +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: [[#NFA+32]] +; SYM-NEXT: SectionLen: 8 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 3 +; SYM-NEXT: SymbolType: XTY_CM (0x3) +; SYM-NEXT: StorageMappingClass: XMC_UL (0x15) +; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) +; SYM-NEXT: } +; SYM-NEXT: } + +; DIS: {{.*}}aix-tls-ld-xcoff-reloc-large.ll.tmp.o: file format aix5coff64-rs6000 +; DIS: Disassembly of section .data: +; DIS: 0000000000000110 (idx: [[#NFA+19]]) _$TLSML[TC]: +; DIS-NEXT: 110: 00 00 00 00 +; DIS-NEXT: 0000000000000110: R_TLSML (idx: [[#NFA+19]]) _$TLSML[TC] +; DIS-NEXT: 114: 00 00 00 00 +; DIS: 0000000000000118 (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE]: +; DIS-NEXT: 118: 00 00 00 00 +; DIS-NEXT: 0000000000000118: R_TLS_LD (idx: [[#NFA+29]]) IThreadLocalVarUninit[UL] +; DIS-NEXT: 11c: 00 00 00 08 +; DIS: 0000000000000120 (idx: [[#NFA+23]]) ThreadLocalVarInit[TE]: +; DIS-NEXT: 120: 00 00 00 00 +; DIS-NEXT: 0000000000000120: R_TLS_LD (idx: [[#NFA+27]]) ThreadLocalVarInit[TL] +; DIS-NEXT: 124: 00 00 00 00 +; DIS: 0000000000000128 (idx: [[#NFA+25]]) IThreadLocalVarUninit2[TE]: +; DIS-NEXT: 128: 00 00 00 00 +; DIS-NEXT: 0000000000000128: R_TLS_LD (idx: [[#NFA+31]]) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 12c: 00 00 00 10 + +; DIS: Disassembly of section .tdata: +; DIS: 0000000000000000 (idx: [[#NFA+27]]) ThreadLocalVarInit[TL]: +; DIS-NEXT: 0: 00 00 00 00 +; DIS-NEXT: 4: 00 00 00 01 + +; DIS: Disassembly of section .tbss: +; DIS: 0000000000000008 (idx: [[#NFA+29]]) IThreadLocalVarUninit[UL]: +; DIS-NEXT: ... +; DIS: 0000000000000010 (idx: [[#NFA+31]]) IThreadLocalVarUninit2[UL]: +; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-local-dynamic.ll b/llvm/test/CodeGen/PowerPC/aix-tls-local-dynamic.ll new file mode 100644 index 0000000..2234933 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-tls-local-dynamic.ll @@ -0,0 +1,396 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: --code-model=small < %s | FileCheck %s --check-prefixes=SMALL64,SMALL +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=LARGE64,LARGE +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ +; RUN: --code-model=small < %s | FileCheck %s --check-prefixes=SMALL32,SMALL +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ +; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=LARGE32,LARGE +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: --code-model=small -O0 < %s | FileCheck %s --check-prefixes=WITHDUP +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: --code-model=small -O1 < %s | FileCheck %s --check-prefixes=NODUP + +@TGInit = thread_local(localdynamic) global i32 42, align 4 +@TGUninit = thread_local(localdynamic) global i32 0, align 4 +@TIInit = internal thread_local(localdynamic) global i32 42, align 4 +@TIUninit = internal thread_local(localdynamic) global i32 0, align 4 +@TWInit = weak thread_local(localdynamic) global i32 42, align 4 +@TWUninit = weak thread_local(localdynamic) global i32 0, align 4 +@x = thread_local(localdynamic) global i32 42, align 4 +@y = thread_local(localdynamic) global i32 42, align 4 + +define i32 @loadTGInit() { +; SMALL-LABEL: loadTGInit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]](2) +; SMALL: lwzx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: loadTGInit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: lwzx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TGInit) + %1 = load i32, ptr %0, align 4 + ret i32 %1 +} + +define void @storeTGInit(i32 noundef signext %i) { +; SMALL-LABEL: storeTGInit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]](2) +; SMALL: stwx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: storeTGInit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TGInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: stwx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TGInit) + store i32 %i, ptr %0, align 4 + ret void +} + +define i32 @loadTGUninit() { +; SMALL-LABEL: loadTGUninit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]](2) +; SMALL: lwzx [[TGInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: loadTGUninit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: lwzx [[TGUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TGUninit) + %1 = load i32, ptr %0, align 4 + ret i32 %1 +} + +define void @storeTGUninit(i32 noundef signext %i) { +; SMALL-LABEL: storeTGUninit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]](2) +; SMALL: stwx [[TGUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: storeTGUninit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TGUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: stwx [[TGUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TGUninit) + store i32 %i, ptr %0, align 4 + ret void +} + +define i32 @loadTIInit() { +; SMALL-LABEL: loadTIInit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]](2) +; SMALL: lwzx [[TIInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: loadTIInit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: lwzx [[TIInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TIInit) + %1 = load i32, ptr %0, align 4 + ret i32 %1 +} + +define void @storeTIInit(i32 noundef signext %i) { +; SMALL-LABEL: storeTIInit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]](2) +; SMALL: stwx [[TIInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: storeTIInit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TIInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: stwx [[TIInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TIInit) + store i32 %i, ptr %0, align 4 + ret void +} + +define i32 @loadTIUninit() { +; SMALL-LABEL: loadTIUninit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]](2) +; SMALL: lwzx [[TIUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: loadTIUninit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: lwzx [[TIUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TIUninit) + %1 = load i32, ptr %0, align 4 + ret i32 %1 +} + +define void @storeTIUninit(i32 noundef signext %i) { +; SMALL-LABEL: storeTIUninit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]](2) +; SMALL: stwx [[TIUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: storeTIUninit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TIUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: stwx [[TIUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TIUninit) + store i32 %i, ptr %0, align 4 + ret void +} + +define i32 @loadTWInit() { +; SMALL-LABEL: loadTWInit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]](2) +; SMALL: lwzx [[TWInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: loadTWInit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: lwzx [[TWInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TWInit) + %1 = load i32, ptr %0, align 4 + ret i32 %1 +} + +define void @storeTWInit(i32 noundef signext %i) { +; SMALL-LABEL: storeTWInit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]](2) +; SMALL: stwx [[TWInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: storeTWInit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TWInitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: stwx [[TWInitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TWInit) + store i32 %i, ptr %0, align 4 + ret void +} + +define i32 @loadTWUninit() { +; SMALL-LABEL: loadTWUninit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]](2) +; SMALL: lwzx [[TWUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: loadTWUninit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: lwzx [[TWUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TWUninit) + %1 = load i32, ptr %0, align 4 + ret i32 %1 +} + +define void @storeTWUninit(i32 noundef signext %i) { +; SMALL-LABEL: storeTWUninit: +; SMALL64: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL32: lwz [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; SMALL: bla .__tls_get_mod[PR] +; SMALL64: ld [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]](2) +; SMALL32: lwz [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]](2) +; SMALL: stwx [[TWUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +; +; LARGE-LABEL: storeTWUninit: +; LARGE64: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE: addis [[OffsetHR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@u(2) +; LARGE32: addis [[ModuleHandleHR:[0-9]+]], [[ModuleHandleL:L..C[0-9]+]]@u(2) +; LARGE64: ld [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE32: lwz [[ModuleHandleR:3]], [[ModuleHandleL]]@l([[ModuleHandleHR]]) +; LARGE: bla .__tls_get_mod[PR] +; LARGE64: ld [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE32: lwz [[OffsetR:[0-9]+]], [[TWUninitL:L..C[0-9]+]]@l([[OffsetHR]]) +; LARGE: stwx [[TWUninitValR:[0-9]+]], [[ModuleHandleR]], [[OffsetR]] +entry: + %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @TWUninit) + store i32 %i, ptr %0, align 4 + ret void +} + +define i32 @DedupTlsGetMod() #0 { +; WITHDUP-LABEL: DedupTlsGetMod: +; WITHDUP: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; WITHDUP-NEXT: bla .__tls_get_mod[PR] +; WITHDUP-NEXT: ld [[OffsetXR:[0-9]+]], [[X:L..C[0-9]+]](2) +; WITHDUP: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; WITHDUP-NEXT: bla .__tls_get_mod[PR] +; WITHDUP: ld [[OffsetYR:[0-9]+]], [[Y:L..C[0-9]+]](2) +; WITHDUP-LABEL: L..DedupTlsGetMod0: +; +; NODUP-LABEL: DedupTlsGetMod: +; NODUP: ld [[ModuleHandleR:3]], [[ModuleHandleL:L..C[0-9]+]](2) +; NODUP-NEXT: bla .__tls_get_mod[PR] +; NODUP-NEXT: ld [[OffsetXR:[0-9]+]], [[X:L..C[0-9]+]](2) +; NODUP-NEXT: ld [[OffsetYR:[0-9]+]], [[Y:L..C[0-9]+]](2) +; NODUP-NEXT: lwzx [[XValR:[0-9]+]], [[ModuleHandleR]], [[OffsetXR]] +; NODUP-NEXT: lwzx [[YValR:[0-9]+]], [[ModuleHandleR]], [[OffsetYR]] +; NODUP-LABEL: L..DedupTlsGetMod0: +entry: + %retval = alloca i32, align 4 + store i32 0, ptr %retval, align 4 + %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x) + %1 = load i32, ptr %0, align 4 + %2 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @y) + %3 = load i32, ptr %2, align 4 + %add = add nsw i32 %1, %3 + ret i32 %add +} + +; SMALL: .extern .__tls_get_mod[PR] +; LARGE: .extern .__tls_get_mod[PR] +; SMALL-NOT: .extern _Renamed..5f24__TLSML[TC] +; LARGE-NOT: .extern _Renamed..5f24__TLSML[TC] + +; SMALL: [[ModuleHandleL]]: +; SMALL-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; SMALL-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; SMALL: [[TGInitL]]: +; SMALL-NEXT: .tc TGInit[TC],TGInit[TL]@ld +; SMALL: [[TGUninitL]]: +; SMALL-NEXT: .tc TGUninit[TC],TGUninit[TL]@ld +; SMALL: [[TIInitL]]: +; SMALL-NEXT: .tc TIInit[TC],TIInit[TL]@ld +; SMALL: [[TIUninitL]]: +; SMALL-NEXT: .tc TIUninit[TC],TIUninit[UL]@ld +; SMALL: [[TWInitL]]: +; SMALL-NEXT: .tc TWInit[TC],TWInit[TL]@ld +; SMALL: [[TWUninitL]]: +; SMALL-NEXT: .tc TWUninit[TC],TWUninit[TL]@ld + +; LARGE64: [[ModuleHandleL]]: +; LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; LARGE64: [[TGInitL]]: +; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]@ld +; +; LARGE32: [[TGInitL]]: +; LARGE32-NEXT: .tc TGInit[TE],TGInit[TL]@ld +; LARGE32: [[ModuleHandleL]]: +; LARGE32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; LARGE32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; +; LARGE: [[TGUninitL]]: +; LARGE-NEXT: .tc TGUninit[TE],TGUninit[TL]@ld +; LARGE: [[TIInitL]]: +; LARGE-NEXT: .tc TIInit[TE],TIInit[TL]@ld +; LARGE: [[TIUninitL]]: +; LARGE-NEXT: .tc TIUninit[TE],TIUninit[UL]@ld +; LARGE: [[TWInitL]]: +; LARGE-NEXT: .tc TWInit[TE],TWInit[TL]@ld +; LARGE: [[TWUninitL]]: +; LARGE-NEXT: .tc TWUninit[TE],TWUninit[TL]@ld + +declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll index 059924f..1f7b497 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll @@ -5,6 +5,7 @@ ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @GInit = global double 1.000000e+00, align 8 +; @TIInit is local-dynamic indeed @TIInit = internal thread_local global i64 1, align 8 @TWInit = weak thread_local global double 1.000000e+00, align 8 @@ -32,7 +33,7 @@ entry: ; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x16 -; RELOC-NEXT: Symbol: .TIInit ([[#NFA+17]]) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -40,7 +41,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1A -; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]]) +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -48,31 +49,31 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1E -; RELOC-NEXT: Symbol: .TIInit ([[#NFA+17]]) +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { -; RELOC-NEXT: Virtual Address: 0x22 -; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]]) +; RELOC-NEXT: Virtual Address: 0x20 +; RELOC-NEXT: Symbol: .__tls_get_mod ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 -; RELOC-NEXT: Length: 16 -; RELOC-NEXT: Type: R_TOCL (0x31) +; RELOC-NEXT: Length: 26 +; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { -; RELOC-NEXT: Virtual Address: 0x24 -; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) +; RELOC-NEXT: Virtual Address: 0x26 +; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 -; RELOC-NEXT: Length: 26 -; RELOC-NEXT: Type: R_RBA (0x18) +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x4E -; RELOC-NEXT: Symbol: .TWInit ([[#NFA+21]]) +; RELOC-NEXT: Symbol: .TWInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -80,7 +81,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x52 -; RELOC-NEXT: Symbol: TWInit ([[#NFA+23]]) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -88,7 +89,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x56 -; RELOC-NEXT: Symbol: .TWInit ([[#NFA+21]]) +; RELOC-NEXT: Symbol: .TWInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -96,7 +97,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x5A -; RELOC-NEXT: Symbol: TWInit ([[#NFA+23]]) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -104,7 +105,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x5C -; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+3]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -112,7 +113,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x66 -; RELOC-NEXT: Symbol: GInit ([[#NFA+25]]) +; RELOC-NEXT: Symbol: GInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -120,7 +121,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x6A -; RELOC-NEXT: Symbol: GInit ([[#NFA+25]]) +; RELOC-NEXT: Symbol: GInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -130,7 +131,7 @@ entry: ; RELOC-NEXT: Section (index: 2) .data { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x90 -; RELOC-NEXT: Symbol: .storesTIInit ([[#NFA+5]]) +; RELOC-NEXT: Symbol: .storesTIInit ([[#NFA+7]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -138,7 +139,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x94 -; RELOC-NEXT: Symbol: TOC ([[#NFA+15]]) +; RELOC-NEXT: Symbol: TOC ([[#NFA+17]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -146,7 +147,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x9C -; RELOC-NEXT: Symbol: .loadsTWInit ([[#NFA+7]]) +; RELOC-NEXT: Symbol: .loadsTWInit ([[#NFA+9]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -154,7 +155,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xA0 -; RELOC-NEXT: Symbol: TOC ([[#NFA+15]]) +; RELOC-NEXT: Symbol: TOC ([[#NFA+17]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -162,23 +163,23 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xA8 -; RELOC-NEXT: Symbol: TIInit ([[#NFA+27]]) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 -; RELOC-NEXT: Type: R_TLSM (0x24) +; RELOC-NEXT: Type: R_TLS_LD (0x22) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xAC -; RELOC-NEXT: Symbol: TIInit ([[#NFA+27]]) +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 -; RELOC-NEXT: Type: R_TLS (0x20) +; RELOC-NEXT: Type: R_TLSML (0x25) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB0 -; RELOC-NEXT: Symbol: TWInit ([[#NFA+29]]) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -186,7 +187,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB4 -; RELOC-NEXT: Symbol: TWInit ([[#NFA+29]]) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -194,7 +195,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB8 -; RELOC-NEXT: Symbol: GInit ([[#NFA+9]]) +; RELOC-NEXT: Symbol: GInit ([[#NFA+11]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -230,7 +231,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: [[#NFA+1]] -; SYM-NEXT: Name: .__tls_get_addr +; SYM-NEXT: Name: .__tls_get_mod ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF ; SYM-NEXT: Type: 0x0 @@ -250,6 +251,26 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: [[#NFA+3]] +; SYM-NEXT: Name: .__tls_get_addr +; SYM-NEXT: Value (RelocatableAddress): 0x0 +; SYM-NEXT: Section: N_UNDEF +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_EXT (0x2) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: [[#NFA+4]] +; SYM-NEXT: SectionLen: 0 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 0 +; SYM-NEXT: SymbolType: XTY_ER (0x0) +; SYM-NEXT: StorageMappingClass: XMC_PR (0x0) +; SYM-NEXT: StabInfoIndex: 0x0 +; SYM-NEXT: StabSectNum: 0x0 +; SYM-NEXT: } +; SYM-NEXT: } +; SYM-NEXT: Symbol { +; SYM-NEXT: Index: [[#NFA+5]] ; SYM-NEXT: Name: ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -257,7 +278,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+4]] +; SYM-NEXT: Index: [[#NFA+6]] ; SYM-NEXT: SectionLen: 132 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -269,7 +290,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+5]] +; SYM-NEXT: Index: [[#NFA+7]] ; SYM-NEXT: Name: .storesTIInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -277,8 +298,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+6]] -; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] +; SYM-NEXT: Index: [[#NFA+8]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+5]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -289,7 +310,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+7]] +; SYM-NEXT: Index: [[#NFA+9]] ; SYM-NEXT: Name: .loadsTWInit ; SYM-NEXT: Value (RelocatableAddress): 0x40 ; SYM-NEXT: Section: .text @@ -297,8 +318,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+8]] -; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] +; SYM-NEXT: Index: [[#NFA+10]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+5]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -309,7 +330,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+9]] +; SYM-NEXT: Index: [[#NFA+11]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data @@ -317,7 +338,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+10]] +; SYM-NEXT: Index: [[#NFA+12]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -329,7 +350,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+11]] +; SYM-NEXT: Index: [[#NFA+13]] ; SYM-NEXT: Name: storesTIInit ; SYM-NEXT: Value (RelocatableAddress): 0x90 ; SYM-NEXT: Section: .data @@ -337,7 +358,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+12]] +; SYM-NEXT: Index: [[#NFA+14]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -349,7 +370,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+13]] +; SYM-NEXT: Index: [[#NFA+15]] ; SYM-NEXT: Name: loadsTWInit ; SYM-NEXT: Value (RelocatableAddress): 0x9C ; SYM-NEXT: Section: .data @@ -357,7 +378,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+14]] +; SYM-NEXT: Index: [[#NFA+16]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -369,7 +390,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+15]] +; SYM-NEXT: Index: [[#NFA+17]] ; SYM-NEXT: Name: TOC ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -377,7 +398,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+16]] +; SYM-NEXT: Index: [[#NFA+18]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -389,15 +410,15 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+17]] -; SYM-NEXT: Name: .TIInit +; SYM-NEXT: Index: [[#NFA+19]] +; SYM-NEXT: Name: TIInit ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data ; SYM-NEXT: Type: 0x0 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+18]] +; SYM-NEXT: Index: [[#NFA+20]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -409,27 +430,27 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+19]] -; SYM-NEXT: Name: TIInit +; SYM-NEXT: Index: [[#NFA+21]] +; SYM-NEXT: Name: _$TLSML ; SYM-NEXT: Value (RelocatableAddress): 0xAC ; SYM-NEXT: Section: .data ; SYM-NEXT: Type: 0x0 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+20]] +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 2 ; SYM-NEXT: SymbolType: XTY_SD (0x1) -; SYM-NEXT: StorageMappingClass: XMC_TE (0x16) +; SYM-NEXT: StorageMappingClass: XMC_TC (0x3) ; SYM-NEXT: StabInfoIndex: 0x0 ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+21]] +; SYM-NEXT: Index: [[#NFA+23]] ; SYM-NEXT: Name: .TWInit ; SYM-NEXT: Value (RelocatableAddress): 0xB0 ; SYM-NEXT: Section: .data @@ -437,7 +458,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+22]] +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -449,7 +470,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+23]] +; SYM-NEXT: Index: [[#NFA+25]] ; SYM-NEXT: Name: TWInit ; SYM-NEXT: Value (RelocatableAddress): 0xB4 ; SYM-NEXT: Section: .data @@ -457,7 +478,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+24]] +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -469,7 +490,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+25]] +; SYM-NEXT: Index: [[#NFA+27]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0xB8 ; SYM-NEXT: Section: .data @@ -477,7 +498,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+26]] +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -489,7 +510,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+27]] +; SYM-NEXT: Index: [[#NFA+29]] ; SYM-NEXT: Name: TIInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -497,7 +518,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+28]] +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -509,7 +530,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+29]] +; SYM-NEXT: Index: [[#NFA+31]] ; SYM-NEXT: Name: TWInit ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tdata @@ -517,7 +538,7 @@ entry: ; SYM-NEXT: StorageClass: C_WEAKEXT (0x6F) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+30]] +; SYM-NEXT: Index: [[#NFA+32]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -536,20 +557,20 @@ entry: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) -; DIS-NEXT: mr 6, 4 ; DIS-NEXT: mr 7, 3 -; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+17]]) .TIInit[TE] -; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 +; DIS-NEXT: mr 6, 4 +; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 8, 2, 0 ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+19]]) TIInit[TE] -; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+17]]) .TIInit[TE] -; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(4) +; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) _$TLSML[TC] +; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 4(3) +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) _$TLSML[TC] +; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0x0 +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_mod[PR] +; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 0(8) ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+19]]) TIInit[TE] -; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] +; DIS-NEXT: stwux 7, 3, 4 ; DIS-NEXT: stw 6, 4(3) -; DIS-NEXT: stw 7, 0(3) ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 @@ -559,20 +580,20 @@ entry: ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) .TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+23]]) .TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+23]]) TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+25]]) TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) .TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+23]]) .TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+23]]) TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+25]]) TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+3]]) .__tls_get_addr[PR] ; DIS-NEXT: lfd 0, 0(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+25]]) GInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+27]]) GInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 16(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+25]]) GInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+27]]) GInit[TE] ; DIS-NEXT: lfd 1, 0(3) ; DIS-NEXT: fadd 1, 0, 1 ; DIS-NEXT: addi 1, 1, 32 @@ -581,42 +602,42 @@ entry: ; DIS-NEXT: blr ; DIS: Disassembly of section .data: -; DIS: 00000088 (idx: [[#NFA+9]]) GInit[RW]: +; DIS: 00000088 (idx: [[#NFA+11]]) GInit[RW]: ; DIS-NEXT: 88: 3f f0 00 00 ; DIS-NEXT: 8c: 00 00 00 00 -; DIS: 00000090 (idx: [[#NFA+11]]) storesTIInit[DS]: +; DIS: 00000090 (idx: [[#NFA+13]]) storesTIInit[DS]: ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 00000090: R_POS (idx: [[#NFA+5]]) .storesTIInit +; DIS-NEXT: 00000090: R_POS (idx: [[#NFA+7]]) .storesTIInit ; DIS-NEXT: 94: 00 00 00 a8 -; DIS-NEXT: 00000094: R_POS (idx: [[#NFA+15]]) TOC[TC0] +; DIS-NEXT: 00000094: R_POS (idx: [[#NFA+17]]) TOC[TC0] ; DIS-NEXT: 98: 00 00 00 00 -; DIS: 0000009c (idx: [[#NFA+13]]) loadsTWInit[DS]: +; DIS: 0000009c (idx: [[#NFA+15]]) loadsTWInit[DS]: ; DIS-NEXT: 9c: 00 00 00 40 -; DIS-NEXT: 0000009c: R_POS (idx: [[#NFA+7]]) .loadsTWInit +; DIS-NEXT: 0000009c: R_POS (idx: [[#NFA+9]]) .loadsTWInit ; DIS-NEXT: a0: 00 00 00 a8 -; DIS-NEXT: 000000a0: R_POS (idx: [[#NFA+15]]) TOC[TC0] +; DIS-NEXT: 000000a0: R_POS (idx: [[#NFA+17]]) TOC[TC0] ; DIS-NEXT: a4: 00 00 00 00 -; DIS: 000000a8 (idx: [[#NFA+17]]) .TIInit[TE]: +; DIS: 000000a8 (idx: [[#NFA+19]]) TIInit[TE]: ; DIS-NEXT: a8: 00 00 00 00 -; DIS-NEXT: 000000a8: R_TLSM (idx: [[#NFA+27]]) TIInit[TL] -; DIS: 000000ac (idx: [[#NFA+19]]) TIInit[TE]: +; DIS-NEXT: 000000a8: R_TLS_LD (idx: [[#NFA+29]]) TIInit[TL] +; DIS: 000000ac (idx: [[#NFA+21]]) _$TLSML[TC]: ; DIS-NEXT: ac: 00 00 00 00 -; DIS-NEXT: 000000ac: R_TLS (idx: [[#NFA+27]]) TIInit[TL] -; DIS: 000000b0 (idx: [[#NFA+21]]) .TWInit[TE]: +; DIS-NEXT: 000000ac: R_TLSML (idx: [[#NFA+21]]) _$TLSML[TC] +; DIS: 000000b0 (idx: [[#NFA+23]]) .TWInit[TE]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 000000b0: R_TLSM (idx: [[#NFA+29]]) TWInit[TL] -; DIS: 000000b4 (idx: [[#NFA+23]]) TWInit[TE]: +; DIS-NEXT: 000000b0: R_TLSM (idx: [[#NFA+31]]) TWInit[TL] +; DIS: 000000b4 (idx: [[#NFA+25]]) TWInit[TE]: ; DIS-NEXT: b4: 00 00 00 08 -; DIS-NEXT: 000000b4: R_TLS (idx: [[#NFA+29]]) TWInit[TL] -; DIS: 000000b8 (idx: [[#NFA+25]]) GInit[TE]: +; DIS-NEXT: 000000b4: R_TLS (idx: [[#NFA+31]]) TWInit[TL] +; DIS: 000000b8 (idx: [[#NFA+27]]) GInit[TE]: ; DIS-NEXT: b8: 00 00 00 88 -; DIS-NEXT: 000000b8: R_POS (idx: [[#NFA+9]]) GInit[RW] +; DIS-NEXT: 000000b8: R_POS (idx: [[#NFA+11]]) GInit[RW] ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: [[#NFA+27]]) TIInit[TL]: +; DIS: 00000000 (idx: [[#NFA+29]]) TIInit[TL]: ; DIS-NEXT: 0: 00 00 00 00 ; DIS-NEXT: 4: 00 00 00 01 -; DIS: 00000008 (idx: [[#NFA+29]]) TWInit[TL]: +; DIS: 00000008 (idx: [[#NFA+31]]) TWInit[TL]: ; DIS-NEXT: 8: 3f f0 00 00 ; DIS-NEXT: c: 00 00 00 00 diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll index eb7a0e2..0a3e763 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll @@ -7,6 +7,7 @@ @const_ivar = constant i32 6, align 4 @GInit = global i32 1, align 4 @TGInit = thread_local global i32 1, align 4 +; @TIUninit is local-dynamic indeed @TIUninit = internal thread_local global i32 0, align 4 ; Function Attrs: nofree norecurse nounwind willreturn writeonly @@ -33,31 +34,31 @@ entry: ; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xE -; RELOC-NEXT: Symbol: .TIUninit ([[#NFA+23]]) +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { -; RELOC-NEXT: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: TIUninit ([[#NFA+25]]) +; RELOC-NEXT: Virtual Address: 0x14 +; RELOC-NEXT: Symbol: .__tls_get_mod ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 -; RELOC-NEXT: Length: 16 -; RELOC-NEXT: Type: R_TOC (0x3) +; RELOC-NEXT: Length: 26 +; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { -; RELOC-NEXT: Virtual Address: 0x18 -; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) +; RELOC-NEXT: Virtual Address: 0x1A +; RELOC-NEXT: Symbol: TIUninit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 -; RELOC-NEXT: Length: 26 -; RELOC-NEXT: Type: R_RBA (0x18) +; RELOC-NEXT: Length: 16 +; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x3A -; RELOC-NEXT: Symbol: .TGInit ([[#NFA+27]]) +; RELOC-NEXT: Symbol: .TGInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -65,7 +66,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x3E -; RELOC-NEXT: Symbol: TGInit ([[#NFA+29]]) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -73,7 +74,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x44 -; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+3]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -81,7 +82,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x4A -; RELOC-NEXT: Symbol: GInit ([[#NFA+31]]) +; RELOC-NEXT: Symbol: GInit ([[#NFA+33]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -91,7 +92,7 @@ entry: ; RELOC-NEXT: Section (index: 2) .data { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x70 -; RELOC-NEXT: Symbol: .storesTIUninit ([[#NFA+5]]) +; RELOC-NEXT: Symbol: .storesTIUninit ([[#NFA+7]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -99,7 +100,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x74 -; RELOC-NEXT: Symbol: TOC ([[#NFA+21]]) +; RELOC-NEXT: Symbol: TOC ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -107,7 +108,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x7C -; RELOC-NEXT: Symbol: .loadsTGInit ([[#NFA+7]]) +; RELOC-NEXT: Symbol: .loadsTGInit ([[#NFA+9]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -115,7 +116,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x80 -; RELOC-NEXT: Symbol: TOC ([[#NFA+21]]) +; RELOC-NEXT: Symbol: TOC ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -123,23 +124,23 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x88 -; RELOC-NEXT: Symbol: TIUninit ([[#NFA+37]]) +; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 -; RELOC-NEXT: Type: R_TLSM (0x24) +; RELOC-NEXT: Type: R_TLSML (0x25) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x8C -; RELOC-NEXT: Symbol: TIUninit ([[#NFA+37]]) +; RELOC-NEXT: Symbol: TIUninit ([[#NFA+39]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 -; RELOC-NEXT: Type: R_TLS (0x20) +; RELOC-NEXT: Type: R_TLS_LD (0x22) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x90 -; RELOC-NEXT: Symbol: TGInit ([[#NFA+35]]) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+37]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -147,7 +148,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x94 -; RELOC-NEXT: Symbol: TGInit ([[#NFA+35]]) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+37]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -155,7 +156,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x98 -; RELOC-NEXT: Symbol: GInit ([[#NFA+15]]) +; RELOC-NEXT: Symbol: GInit ([[#NFA+17]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -178,9 +179,9 @@ entry: ; SYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYM-NEXT: StorageClass: C_FILE (0x67) ; SYM-NEXT: NumberOfAuxEntries: 2 -; SYM: Symbol { +; SYM: Symbol { ; SYM-NEXT: Index: [[#NFA+1]] -; SYM-NEXT: Name: .__tls_get_addr +; SYM-NEXT: Name: .__tls_get_mod ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF ; SYM-NEXT: Type: 0x0 @@ -200,6 +201,26 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: [[#NFA+3]] +; SYM-NEXT: Name: .__tls_get_addr +; SYM-NEXT: Value (RelocatableAddress): 0x0 +; SYM-NEXT: Section: N_UNDEF +; SYM-NEXT: Type: 0x0 +; SYM-NEXT: StorageClass: C_EXT (0x2) +; SYM-NEXT: NumberOfAuxEntries: 1 +; SYM-NEXT: CSECT Auxiliary Entry { +; SYM-NEXT: Index: 6 +; SYM-NEXT: SectionLen: 0 +; SYM-NEXT: ParameterHashIndex: 0x0 +; SYM-NEXT: TypeChkSectNum: 0x0 +; SYM-NEXT: SymbolAlignmentLog2: 0 +; SYM-NEXT: SymbolType: XTY_ER (0x0) +; SYM-NEXT: StorageMappingClass: XMC_PR (0x0) +; SYM-NEXT: StabInfoIndex: 0x0 +; SYM-NEXT: StabSectNum: 0x0 +; SYM-NEXT: } +; SYM-NEXT: } +; SYM-NEXT: Symbol { +; SYM-NEXT: Index: [[#NFA+5]] ; SYM-NEXT: Name: ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -207,7 +228,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+4]] +; SYM-NEXT: Index: [[#NFA+6]] ; SYM-NEXT: SectionLen: 104 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -219,7 +240,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+5]] +; SYM-NEXT: Index: [[#NFA+7]] ; SYM-NEXT: Name: .storesTIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -227,8 +248,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+6]] -; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] +; SYM-NEXT: Index: [[#NFA+8]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+5]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -239,7 +260,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+7]] +; SYM-NEXT: Index: [[#NFA+9]] ; SYM-NEXT: Name: .loadsTGInit ; SYM-NEXT: Value (RelocatableAddress): 0x30 ; SYM-NEXT: Section: .text @@ -247,8 +268,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+8]] -; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] +; SYM-NEXT: Index: [[#NFA+10]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+5]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -259,7 +280,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+9]] +; SYM-NEXT: Index: [[#NFA+11]] ; SYM-NEXT: Name: .rodata ; SYM-NEXT: Value (RelocatableAddress): 0x68 ; SYM-NEXT: Section: .text @@ -267,7 +288,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+10]] +; SYM-NEXT: Index: [[#NFA+12]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -279,7 +300,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+11]] +; SYM-NEXT: Index: [[#NFA+13]] ; SYM-NEXT: Name: const_ivar ; SYM-NEXT: Value (RelocatableAddress): 0x68 ; SYM-NEXT: Section: .text @@ -287,8 +308,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+12]] -; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+9]] +; SYM-NEXT: Index: [[#NFA+14]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+11]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -299,7 +320,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+13]] +; SYM-NEXT: Index: [[#NFA+15]] ; SYM-NEXT: Name: .data ; SYM-NEXT: Value (RelocatableAddress): 0x6C ; SYM-NEXT: Section: .data @@ -307,7 +328,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+14]] +; SYM-NEXT: Index: [[#NFA+16]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -319,7 +340,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+15]] +; SYM-NEXT: Index: [[#NFA+17]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x6C ; SYM-NEXT: Section: .data @@ -327,8 +348,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+16]] -; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+13]] +; SYM-NEXT: Index: [[#NFA+18]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+15]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -339,7 +360,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+17]] +; SYM-NEXT: Index: [[#NFA+19]] ; SYM-NEXT: Name: storesTIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x70 ; SYM-NEXT: Section: .data @@ -347,7 +368,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+18]] +; SYM-NEXT: Index: [[#NFA+20]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -359,7 +380,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+19]] +; SYM-NEXT: Index: [[#NFA+21]] ; SYM-NEXT: Name: loadsTGInit ; SYM-NEXT: Value (RelocatableAddress): 0x7C ; SYM-NEXT: Section: .data @@ -367,7 +388,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+20]] +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -379,7 +400,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+21]] +; SYM-NEXT: Index: [[#NFA+23]] ; SYM-NEXT: Name: TOC ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data @@ -387,7 +408,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+22]] +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -399,15 +420,15 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+23]] -; SYM-NEXT: Name: .TIUninit +; SYM-NEXT: Index: [[#NFA+25]] +; SYM-NEXT: Name: _$TLSML ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data ; SYM-NEXT: Type: 0x0 ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+24]] +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -419,7 +440,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+25]] +; SYM-NEXT: Index: [[#NFA+27]] ; SYM-NEXT: Name: TIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x8C ; SYM-NEXT: Section: .data @@ -427,7 +448,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+26]] +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -439,7 +460,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+27]] +; SYM-NEXT: Index: [[#NFA+29]] ; SYM-NEXT: Name: .TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x90 ; SYM-NEXT: Section: .data @@ -447,7 +468,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+28]] +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -459,7 +480,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+29]] +; SYM-NEXT: Index: [[#NFA+31]] ; SYM-NEXT: Name: TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x94 ; SYM-NEXT: Section: .data @@ -467,7 +488,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+30]] +; SYM-NEXT: Index: [[#NFA+32]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -479,7 +500,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+31]] +; SYM-NEXT: Index: [[#NFA+33]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x98 ; SYM-NEXT: Section: .data @@ -487,7 +508,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+32]] +; SYM-NEXT: Index: [[#NFA+34]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -499,7 +520,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+33]] +; SYM-NEXT: Index: [[#NFA+35]] ; SYM-NEXT: Name: .tdata ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -507,7 +528,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+34]] +; SYM-NEXT: Index: [[#NFA+36]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -519,7 +540,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+35]] +; SYM-NEXT: Index: [[#NFA+37]] ; SYM-NEXT: Name: TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -527,8 +548,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+36]] -; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+33]] +; SYM-NEXT: Index: [[#NFA+38]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+35]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -539,7 +560,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: [[#NFA+37]] +; SYM-NEXT: Index: [[#NFA+39]] ; SYM-NEXT: Name: TIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x4 ; SYM-NEXT: Section: .tbss @@ -547,7 +568,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: [[#NFA+38]] +; SYM-NEXT: Index: [[#NFA+40]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -562,34 +583,34 @@ entry: ; DIS: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: [[#NFA+5]]) .storesTIUninit: +; DIS: 00000000 (idx: [[#NFA+7]]) .storesTIUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: mr 6, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) .TIUninit[TC] -; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+25]]) TIUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+25]]) _$TLSML[TC] ; DIS-NEXT: stw 0, 40(1) -; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] -; DIS-NEXT: stw 6, 0(3) +; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0x0 +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_mod[PR] +; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(2) +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+27]]) TIUninit[TC] +; DIS-NEXT: stwx 6, 3, 4 ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000030 (idx: [[#NFA+7]]) .loadsTGInit: +; DIS: 00000030 (idx: [[#NFA+9]]) .loadsTGInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+27]]) .TGInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+29]]) .TGInit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+29]]) TGInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+31]]) TGInit[TC] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+3]]) .__tls_get_addr[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 16(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+31]]) GInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+33]]) GInit[TC] ; DIS-NEXT: lwz 3, 0(3) ; DIS-NEXT: lwz 4, 0(4) ; DIS-NEXT: add 3, 4, 3 @@ -597,46 +618,46 @@ entry: ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000068 (idx: [[#NFA+11]]) const_ivar: +; DIS: 00000068 (idx: [[#NFA+13]]) const_ivar: ; DIS-NEXT: 68: 00 00 00 06 ; DIS: Disassembly of section .data: -; DIS: 0000006c (idx: [[#NFA+15]]) GInit: +; DIS: 0000006c (idx: [[#NFA+17]]) GInit: ; DIS-NEXT: 6c: 00 00 00 01 -; DIS: 00000070 (idx: [[#NFA+17]]) storesTIUninit[DS]: +; DIS: 00000070 (idx: [[#NFA+19]]) storesTIUninit[DS]: ; DIS-NEXT: 70: 00 00 00 00 -; DIS-NEXT: 00000070: R_POS (idx: [[#NFA+5]]) .storesTIUninit +; DIS-NEXT: 00000070: R_POS (idx: [[#NFA+7]]) .storesTIUninit ; DIS-NEXT: 74: 00 00 00 88 -; DIS-NEXT: 00000074: R_POS (idx: [[#NFA+21]]) TOC[TC0] +; DIS-NEXT: 00000074: R_POS (idx: [[#NFA+23]]) TOC[TC0] ; DIS-NEXT: 78: 00 00 00 00 -; DIS: 0000007c (idx: [[#NFA+19]]) loadsTGInit[DS]: +; DIS: 0000007c (idx: [[#NFA+21]]) loadsTGInit[DS]: ; DIS-NEXT: 7c: 00 00 00 30 -; DIS-NEXT: 0000007c: R_POS (idx: [[#NFA+7]]) .loadsTGInit +; DIS-NEXT: 0000007c: R_POS (idx: [[#NFA+9]]) .loadsTGInit ; DIS-NEXT: 80: 00 00 00 88 -; DIS-NEXT: 00000080: R_POS (idx: [[#NFA+21]]) TOC[TC0] +; DIS-NEXT: 00000080: R_POS (idx: [[#NFA+23]]) TOC[TC0] ; DIS-NEXT: 84: 00 00 00 00 -; DIS: 00000088 (idx: [[#NFA+23]]) .TIUninit[TC]: +; DIS: 00000088 (idx: [[#NFA+25]]) _$TLSML[TC]: ; DIS-NEXT: 88: 00 00 00 00 -; DIS-NEXT: 00000088: R_TLSM (idx: [[#NFA+37]]) TIUninit[UL] -; DIS: 0000008c (idx: [[#NFA+25]]) TIUninit[TC]: +; DIS-NEXT: 00000088: R_TLSML (idx: [[#NFA+25]]) _$TLSML[TC] +; DIS: 0000008c (idx: [[#NFA+27]]) TIUninit[TC]: ; DIS-NEXT: 8c: 00 00 00 04 -; DIS-NEXT: 0000008c: R_TLS (idx: [[#NFA+37]]) TIUninit[UL] -; DIS: 00000090 (idx: [[#NFA+27]]) .TGInit[TC]: +; DIS-NEXT: 0000008c: R_TLS_LD (idx: [[#NFA+39]]) TIUninit[UL] +; DIS: 00000090 (idx: [[#NFA+29]]) .TGInit[TC]: ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 00000090: R_TLSM (idx: [[#NFA+35]]) TGInit -; DIS: 00000094 (idx: [[#NFA+29]]) TGInit[TC]: +; DIS-NEXT: 00000090: R_TLSM (idx: [[#NFA+37]]) TGInit +; DIS: 00000094 (idx: [[#NFA+31]]) TGInit[TC]: ; DIS-NEXT: 94: 00 00 00 00 -; DIS-NEXT: 00000094: R_TLS (idx: [[#NFA+35]]) TGInit -; DIS: 00000098 (idx: [[#NFA+31]]) GInit[TC]: +; DIS-NEXT: 00000094: R_TLS (idx: [[#NFA+37]]) TGInit +; DIS: 00000098 (idx: [[#NFA+33]]) GInit[TC]: ; DIS-NEXT: 98: 00 00 00 6c -; DIS-NEXT: 00000098: R_POS (idx: [[#NFA+15]]) GInit +; DIS-NEXT: 00000098: R_POS (idx: [[#NFA+17]]) GInit ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: [[#NFA+35]]) TGInit: +; DIS: 00000000 (idx: [[#NFA+37]]) TGInit: ; DIS-NEXT: 0: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 00000004 (idx: [[#NFA+37]]) TIUninit[UL]: +; DIS: 00000004 (idx: [[#NFA+39]]) TIUninit[UL]: ; DIS-NEXT: ... attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-spe,-vsx" } |