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| author | Craig Topper <craig.topper@sifive.com> | 2024-06-24 23:30:15 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2024-06-24 23:45:53 -0700 |
| commit | 41f8e6d3ea57315e619ab9f71e1663095f4ed59d (patch) | |
| tree | 53675ed42cdff1b2761ed20bee46068f5ea3b3ed | |
| parent | f1e0657d144f5a3cfef4b625d0f875f4dacd21d1 (diff) | |
| download | llvm-41f8e6d3ea57315e619ab9f71e1663095f4ed59d.zip llvm-41f8e6d3ea57315e619ab9f71e1663095f4ed59d.tar.gz llvm-41f8e6d3ea57315e619ab9f71e1663095f4ed59d.tar.bz2 | |
[RISCV][GISel] Fix test case order in fp-arith.mir. NFC
The fadd_f64 test was in the middle of some f32 tests.
| -rw-r--r-- | llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir index 78bb91d..037647a 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir @@ -193,30 +193,6 @@ body: | ... --- -name: fadd_f64 -legalized: true -regBankSelected: true -tracksRegLiveness: true -body: | - bb.0: - liveins: $f10_d, $f11_d - - ; CHECK-LABEL: name: fadd_f64 - ; CHECK: liveins: $f10_d, $f11_d - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d - ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7 - ; CHECK-NEXT: $f10_d = COPY [[FADD_D]] - ; CHECK-NEXT: PseudoRET implicit $f10_d - %0:fprb(s64) = COPY $f10_d - %1:fprb(s64) = COPY $f11_d - %2:fprb(s64) = G_FADD %0, %1 - $f10_d = COPY %2(s64) - PseudoRET implicit $f10_d - -... ---- name: fmaxnum_f32 legalized: true regBankSelected: true @@ -289,6 +265,30 @@ body: | ... --- +name: fadd_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fadd_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FADD_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = G_FADD %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- name: fsub_f64 legalized: true regBankSelected: true |