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| author | Craig Topper <craig.topper@sifive.com> | 2024-07-05 19:49:07 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2024-07-05 19:55:28 -0700 |
| commit | 0b9f2847da79298ed09c29493245113f02b32d9f (patch) | |
| tree | 23f98b496307597f0d42cc9eb043ac001684c176 | |
| parent | 6337fdcc520e8f948bef23b361c75edeb32ed015 (diff) | |
| download | llvm-0b9f2847da79298ed09c29493245113f02b32d9f.zip llvm-0b9f2847da79298ed09c29493245113f02b32d9f.tar.gz llvm-0b9f2847da79298ed09c29493245113f02b32d9f.tar.bz2 | |
[RISCV] Remove unused check-prefixes. NFC
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll index def8fb5..f7477da 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32VB +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVA22U64 @@ -1502,6 +1502,3 @@ define <8 x double> @buildvec_v8f64_zvl512(double %e0, double %e1, double %e2, d %v7 = insertelement <8 x double> %v6, double %e7, i64 7 ret <8 x double> %v7 } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; RV32V: {{.*}} -; RV32VB: {{.*}} |