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| author | Amara Emerson <amara@apple.com> | 2024-04-26 15:23:03 -0700 |
|---|---|---|
| committer | Amara Emerson <amara@apple.com> | 2024-04-26 15:26:19 -0700 |
| commit | eb3030acd0bd3eaea85707cf00872e88d20f4664 (patch) | |
| tree | 36536b5c3423db94e9af9be0a168b3c5a8d7ecb1 | |
| parent | fefac5d5458a00b28860e0193928b30be85413cd (diff) | |
| download | llvm-eb3030acd0bd3eaea85707cf00872e88d20f4664.zip llvm-eb3030acd0bd3eaea85707cf00872e88d20f4664.tar.gz llvm-eb3030acd0bd3eaea85707cf00872e88d20f4664.tar.bz2 | |
[AArch64][GlobalISel] Fix legalizer crash trying to legalize <16 x i32> = G_BITCAST i512
Trying to do fewerElements on this results in an assert.
rdar://126373053
| -rw-r--r-- | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir | 50 |
2 files changed, 53 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index f42c415..f654065 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -740,6 +740,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) .legalForCartesianProduct({s32, v2s16, v4s8}) .legalForCartesianProduct({s64, v8s8, v4s16, v2s32}) .legalForCartesianProduct({s128, v16s8, v8s16, v4s32, v2s64, v2p0}) + .lowerIf([=](const LegalityQuery &Query) { + return Query.Types[0].isVector() != Query.Types[1].isVector(); + }) .moreElementsToNextPow2(0) .clampNumElements(0, v8s8, v16s8) .clampNumElements(0, v4s16, v8s16) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir new file mode 100644 index 0000000..e3a633c --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s +--- +name: scalar_to_oversize_vector +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: scalar_to_oversize_vector + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV4]](s32), [[UV5]](s32), [[UV6]](s32), [[UV7]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV12]](s32), [[UV13]](s32), [[UV14]](s32), [[UV15]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s32>), [[C1]](p0) :: (store (<4 x s32>), align 64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 16 + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<4 x s32>), [[C2]](p0) :: (store (<4 x s32>) into unknown-address + 16) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(p0) = G_CONSTANT i64 32 + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR2]](<4 x s32>), [[C3]](p0) :: (store (<4 x s32>) into unknown-address + 32, align 32) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(p0) = G_CONSTANT i64 48 + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR3]](<4 x s32>), [[C4]](p0) :: (store (<4 x s32>) into unknown-address + 48) + ; CHECK-NEXT: G_BR %bb.1 + bb.1: + %0:_(s512) = G_CONSTANT i512 0 + %2:_(p0) = G_CONSTANT i64 0 + G_BR %bb.2 + + bb.2: + %4:_(s512) = G_CONSTANT i512 0 + %1:_(<16 x s32>) = G_BITCAST %4(s512) + %3:_(p0) = G_CONSTANT i64 0 + G_STORE %1(<16 x s32>), %3(p0) :: (store (<16 x s32>)) + G_BR %bb.2 + +... |