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author | Fangrui Song <i@maskray.me> | 2023-12-08 15:09:22 -0800 |
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committer | Fangrui Song <i@maskray.me> | 2023-12-08 15:09:22 -0800 |
commit | 9810fe1a91eb9ce18246fb1528232a539dbd37fc (patch) | |
tree | 7c857f078e62a591a5cc1eee400a9418faf6296a | |
parent | 44dc1e0baae7c4b8a02ba06dcf396d3d452aa873 (diff) | |
download | llvm-9810fe1a91eb9ce18246fb1528232a539dbd37fc.zip llvm-9810fe1a91eb9ce18246fb1528232a539dbd37fc.tar.gz llvm-9810fe1a91eb9ce18246fb1528232a539dbd37fc.tar.bz2 |
[MCSchedule] Simplify and remove a C++20-deprecated is_pod call. NFC
-rw-r--r-- | llvm/include/llvm/CodeGen/TargetSchedule.h | 2 | ||||
-rw-r--r-- | llvm/include/llvm/MC/MCInstrItineraries.h | 4 | ||||
-rw-r--r-- | llvm/include/llvm/MC/MCSchedule.h | 1 | ||||
-rw-r--r-- | llvm/lib/MC/MCSchedule.cpp | 6 | ||||
-rw-r--r-- | llvm/lib/MC/MCSubtargetInfo.cpp | 4 |
5 files changed, 8 insertions, 9 deletions
diff --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h index 3d39798..bfe4234 100644 --- a/llvm/include/llvm/CodeGen/TargetSchedule.h +++ b/llvm/include/llvm/CodeGen/TargetSchedule.h @@ -46,7 +46,7 @@ class TargetSchedModel { unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const; public: - TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {} + TargetSchedModel() : SchedModel(MCSchedModel::Default) {} /// Initialize the machine model for instruction scheduling. /// diff --git a/llvm/include/llvm/MC/MCInstrItineraries.h b/llvm/include/llvm/MC/MCInstrItineraries.h index d1c2e78..6b29686 100644 --- a/llvm/include/llvm/MC/MCInstrItineraries.h +++ b/llvm/include/llvm/MC/MCInstrItineraries.h @@ -110,8 +110,8 @@ struct InstrItinerary { class InstrItineraryData { public: MCSchedModel SchedModel = - MCSchedModel::GetDefaultSchedModel(); ///< Basic machine properties. - const InstrStage *Stages = nullptr; ///< Array of stages selected + MCSchedModel::Default; ///< Basic machine properties. + const InstrStage *Stages = nullptr; ///< Array of stages selected const unsigned *OperandCycles = nullptr; ///< Array of operand cycles selected const unsigned *Forwardings = nullptr; ///< Array of pipeline forwarding paths const InstrItinerary *Itineraries = diff --git a/llvm/include/llvm/MC/MCSchedule.h b/llvm/include/llvm/MC/MCSchedule.h index 98ebe42..5a6471a 100644 --- a/llvm/include/llvm/MC/MCSchedule.h +++ b/llvm/include/llvm/MC/MCSchedule.h @@ -390,7 +390,6 @@ struct MCSchedModel { unsigned WriteResourceIdx = 0); /// Returns the default initialized model. - static const MCSchedModel &GetDefaultSchedModel() { return Default; } static const MCSchedModel Default; }; diff --git a/llvm/lib/MC/MCSchedule.cpp b/llvm/lib/MC/MCSchedule.cpp index 990a693..4f71258 100644 --- a/llvm/lib/MC/MCSchedule.cpp +++ b/llvm/lib/MC/MCSchedule.cpp @@ -20,8 +20,8 @@ using namespace llvm; -static_assert(std::is_pod<MCSchedModel>::value, - "We shouldn't have a static constructor here"); +static_assert(std::is_trivial_v<MCSchedModel>, + "MCSchedModel is required to be a trivial type"); const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth, DefaultMicroOpBufferSize, DefaultLoopMicroOpBufferSize, @@ -30,7 +30,7 @@ const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth, DefaultMispredictPenalty, false, true, - false /*EnableIntervals*/, + /*EnableIntervals=*/false, 0, nullptr, nullptr, diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp index 8ee823e..cf3aba1 100644 --- a/llvm/lib/MC/MCSubtargetInfo.cpp +++ b/llvm/lib/MC/MCSubtargetInfo.cpp @@ -214,7 +214,7 @@ void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, if (!TuneCPU.empty()) CPUSchedModel = &getSchedModelForCPU(TuneCPU); else - CPUSchedModel = &MCSchedModel::GetDefaultSchedModel(); + CPUSchedModel = &MCSchedModel::Default; } void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef TuneCPU, @@ -319,7 +319,7 @@ const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { errs() << "'" << CPU << "' is not a recognized processor for this target" << " (ignoring processor)\n"; - return MCSchedModel::GetDefaultSchedModel(); + return MCSchedModel::Default; } assert(CPUEntry->SchedModel && "Missing processor SchedModel value"); return *CPUEntry->SchedModel; |