diff options
author | Craig Topper <craig.topper@sifive.com> | 2023-12-08 10:38:59 -0800 |
---|---|---|
committer | Craig Topper <craig.topper@sifive.com> | 2023-12-08 10:47:31 -0800 |
commit | 2b36d85a3e000793863c67d48880f23c1e6f95eb (patch) | |
tree | 264d20ad650c1928be6f44e4c46b2ab4509a0e70 | |
parent | 478d093e1b58e1054f549aec4be5d27e26bdd062 (diff) | |
download | llvm-2b36d85a3e000793863c67d48880f23c1e6f95eb.zip llvm-2b36d85a3e000793863c67d48880f23c1e6f95eb.tar.gz llvm-2b36d85a3e000793863c67d48880f23c1e6f95eb.tar.bz2 |
[RISCV] Update comment for AVL operand in pseudo instructions. NFC
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 127d308..5e06422 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -81,9 +81,9 @@ def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S", def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB", SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>; -// Operand that is allowed to be a register or a 5 bit immediate. -// This allows us to pick between VSETIVLI and VSETVLI opcodes using the same -// pseudo instructions. +// Operand that is allowed to be a register other than X0, a 5 bit unsigned +// immediate, or -1. -1 means VLMAX. This allows us to pick between VSETIVLI and +// VSETVLI opcodes using the same pseudo instructions. def AVL : RegisterOperand<GPRNoX0> { let OperandNamespace = "RISCVOp"; let OperandType = "OPERAND_AVL"; |