diff options
| author | Jay Foad <jay.foad@amd.com> | 2024-06-20 12:30:34 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-20 12:30:34 +0100 |
| commit | 90779fdc19dc15099231d6ebc39d9d76991d2d43 (patch) | |
| tree | 6c54dea5ed973d382e9f2e99736d362b179e4875 | |
| parent | 84428dafc0941e3a31303fa1b286835ab2b8e234 (diff) | |
| download | llvm-90779fdc19dc15099231d6ebc39d9d76991d2d43.zip llvm-90779fdc19dc15099231d6ebc39d9d76991d2d43.tar.gz llvm-90779fdc19dc15099231d6ebc39d9d76991d2d43.tar.bz2 | |
[AMDGPU] Preserve chain when selecting llvm.amdgcn.pops.exiting.wave.id (#96167)
Without this SelectionDAG could fail assertions when using the intrinsic
in a non-entry BB.
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll | 39 |
2 files changed, 41 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index d60c62a..5b616d8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -2554,7 +2554,8 @@ void AMDGPUDAGToDAGISel::SelectPOPSExitingWaveID(SDNode *N) { // intrinsic is IntrReadMem/IntrWriteMem but the instruction is not marked // mayLoad/mayStore and tablegen complains about the mismatch. SDValue Reg = CurDAG->getRegister(AMDGPU::SRC_POPS_EXITING_WAVE_ID, MVT::i32); - CurDAG->SelectNodeTo(N, AMDGPU::S_MOV_B32, N->getVTList(), Reg); + SDValue Chain = N->getOperand(0); + CurDAG->SelectNodeTo(N, AMDGPU::S_MOV_B32, N->getVTList(), {Reg, Chain}); } static unsigned gwsIntrinToOpcode(unsigned IntrID) { diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll index 4927c2f..de9e407 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll @@ -32,3 +32,42 @@ define amdgpu_ps void @test(ptr addrspace(1) inreg %ptr) { store i32 %id, ptr addrspace(1) %ptr ret void } + +define amdgpu_ps void @test_loop() { +; SDAG-LABEL: test_loop: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id +; SDAG-NEXT: .LBB1_1: ; %loop +; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; SDAG-NEXT: s_cmp_eq_u32 s0, 0 +; SDAG-NEXT: s_cbranch_scc1 .LBB1_1 +; SDAG-NEXT: ; %bb.2: ; %exit +; SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: test_loop: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id +; GFX9-GISEL-NEXT: .LBB1_1: ; %loop +; GFX9-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_cmp_eq_u32 s0, 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX9-GISEL-NEXT: ; %bb.2: ; %exit +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX10-GISEL-LABEL: test_loop: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id +; GFX10-GISEL-NEXT: .LBB1_1: ; %loop +; GFX10-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-GISEL-NEXT: s_cmp_eq_u32 s0, 0 +; GFX10-GISEL-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX10-GISEL-NEXT: ; %bb.2: ; %exit +; GFX10-GISEL-NEXT: s_endpgm + br label %loop +loop: + %id = call i32 @llvm.amdgcn.pops.exiting.wave.id() + %cond = icmp eq i32 %id, 0 + br i1 %cond, label %loop, label %exit +exit: + ret void +} |