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author | Chen Zheng <czhengsz@cn.ibm.com> | 2024-03-07 20:19:26 -0500 |
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committer | Chen Zheng <czhengsz@cn.ibm.com> | 2024-03-07 20:22:26 -0500 |
commit | e7a22e72de79352c4639664f1ac678555a4c20e4 (patch) | |
tree | 1b0a1948519d8b57b466d7a160ead6123887e150 | |
parent | ddaf040ea924b1bdd4e093f583018c262da3cc7f (diff) | |
download | llvm-e7a22e72de79352c4639664f1ac678555a4c20e4.zip llvm-e7a22e72de79352c4639664f1ac678555a4c20e4.tar.gz llvm-e7a22e72de79352c4639664f1ac678555a4c20e4.tar.bz2 |
[PPC] precommit cases for issue 74915
-rw-r--r-- | llvm/test/CodeGen/PowerPC/pr74951.ll | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/pr74951.ll b/llvm/test/CodeGen/PowerPC/pr74951.ll new file mode 100644 index 0000000..a0d19fc --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr74951.ll @@ -0,0 +1,54 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -verify-machineinstrs -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s + +%struct.anon = type { i32 } + +@b = local_unnamed_addr global %struct.anon { i32 -1 }, align 4 +@g = local_unnamed_addr global [1 x i1] zeroinitializer, align 1 + +define noundef signext i32 @main() { +; CHECK-LABEL: main: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ld r3, L..C0(r2) # @b +; CHECK-NEXT: lwz r3, 0(r3) +; CHECK-NEXT: extsw r4, r3 +; CHECK-NEXT: neg r4, r4 +; CHECK-NEXT: andi. r5, r3, 65535 +; CHECK-NEXT: rldicl r4, r4, 1, 63 +; CHECK-NEXT: bne cr0, L..BB0_4 +; CHECK-NEXT: # %bb.1: # %lor.rhs.i.i +; CHECK-NEXT: xori r5, r4, 1 +; CHECK-NEXT: cmpw r3, r5 +; CHECK-NEXT: crnot 4*cr5+lt, eq +; CHECK-NEXT: li r3, 1 +; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_3 +; CHECK-NEXT: # %bb.2: # %lor.rhs.i.i +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: L..BB0_3: # %lor.rhs.i.i +; CHECK-NEXT: ld r5, L..C1(r2) # @g +; CHECK-NEXT: stb r3, 0(r5) +; CHECK-NEXT: L..BB0_4: # %g.exit +; CHECK-NEXT: ld r5, L..C1(r2) # @g +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: stb r4, 0(r5) +; CHECK-NEXT: blr +entry: + %0 = load i32, ptr @b, align 4 + %conv4.i = sext i32 %0 to i64 + %cmp.i = icmp slt i32 %0, 1 + %conv.i = zext i1 %cmp.i to i32 + %cmp1.i = icmp ne i32 %0, %conv.i + %conv3.i = trunc i32 %0 to i16 + %tobool.not.i.i = icmp eq i16 %conv3.i, 0 + br i1 %tobool.not.i.i, label %lor.rhs.i.i, label %g.exit + +lor.rhs.i.i: ; preds = %entry + store i1 %cmp1.i, ptr @g, align 1 + br label %g.exit + +g.exit: ; preds = %lor.end.i.i + %4 = trunc i64 %conv4.i to i32 + %cmp.i9.i = icmp sgt i32 %4, 0 + store i1 %cmp.i9.i, ptr @g, align 1 + ret i32 0 +} |