[RISCV] Rename rvp-ext-rv32/64.ll to rvp-simd-32/64.ll. Shorten check prefixes. NFC (#194770)

The rv32/rv64 here were the length of the vector types. The
rvp-ext-rv32.ll test has rv32 and rv64 RUN lines. Rename to make this
clearer.

I want to add rv32 RUN lines to the rvp-simd-64.ll, but we need to fix
some crashes first.

2 files changed, 564 insertions, 564 deletions

diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index cb466e4502cf..34239e31504e 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m,+zbb \
 ; RUN:   -verify-machineinstrs < %s | \
-; RUN:   FileCheck --check-prefixes=CHECK,CHECK-RV32 %s
+; RUN:   FileCheck --check-prefixes=CHECK,RV32 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
 ; RUN:   -verify-machineinstrs < %s | \
-; RUN:   FileCheck --check-prefixes=CHECK,CHECK-RV64 %s
+; RUN:   FileCheck --check-prefixes=CHECK,RV64 %s
 
 ; Test basic add/sub operations for v2i16
 define <2 x i16> @test_padd_h(<2 x i16> %a, <2 x i16> %b) {
@@ -551,71 +551,71 @@ define i8 @test_extract_vector_8_elem1(<4 x i8> %a) {
 }
 
 define <2 x i16> @test_insert_vector_16(<2 x i16> %a, i16 %val) {
-; CHECK-RV32-LABEL: test_insert_vector_16:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a0, a0, 16
-; CHECK-RV32-NEXT:    pack a0, a1, a0
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_insert_vector_16:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a0, a0, 16
+; RV32-NEXT:    pack a0, a1, a0
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_insert_vector_16:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srli a0, a0, 16
-; CHECK-RV64-NEXT:    ppaire.h a0, a1, a0
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_insert_vector_16:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srli a0, a0, 16
+; RV64-NEXT:    ppaire.h a0, a1, a0
+; RV64-NEXT:    ret
   %res = insertelement <2 x i16> %a, i16 %val, i32 0
   ret <2 x i16> %res
 }
 
 define <2 x i16> @test_insert_vector_16_elem1(<2 x i16> %a, i16 %val) {
-; CHECK-RV32-LABEL: test_insert_vector_16_elem1:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_insert_vector_16_elem1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_insert_vector_16_elem1:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_insert_vector_16_elem1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = insertelement <2 x i16> %a, i16 %val, i32 1
   ret <2 x i16> %res
 }
 
 define <4 x i8> @test_insert_vector_8(<4 x i8> %a, i8 %val) {
-; CHECK-RV32-LABEL: test_insert_vector_8:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    li a2, 255
-; CHECK-RV32-NEXT:    mvm a0, a1, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_insert_vector_8:
+; RV32:       # %bb.0:
+; RV32-NEXT:    li a2, 255
+; RV32-NEXT:    mvm a0, a1, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_insert_vector_8:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srli a2, a0, 8
-; CHECK-RV64-NEXT:    srli a3, a0, 24
-; CHECK-RV64-NEXT:    srli a0, a0, 16
-; CHECK-RV64-NEXT:    ppaire.b a0, a0, a3
-; CHECK-RV64-NEXT:    ppaire.b a1, a1, a2
-; CHECK-RV64-NEXT:    ppaire.h a0, a1, a0
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_insert_vector_8:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srli a2, a0, 8
+; RV64-NEXT:    srli a3, a0, 24
+; RV64-NEXT:    srli a0, a0, 16
+; RV64-NEXT:    ppaire.b a0, a0, a3
+; RV64-NEXT:    ppaire.b a1, a1, a2
+; RV64-NEXT:    ppaire.h a0, a1, a0
+; RV64-NEXT:    ret
   %res = insertelement <4 x i8> %a, i8 %val, i32 0
   ret <4 x i8> %res
 }
 
 define <4 x i8> @test_insert_vector_8_elem2(<4 x i8> %a, i8 %val) {
-; CHECK-RV32-LABEL: test_insert_vector_8_elem2:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    slli a1, a1, 16
-; CHECK-RV32-NEXT:    lui a2, 4080
-; CHECK-RV32-NEXT:    mvm a0, a1, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_insert_vector_8_elem2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    slli a1, a1, 16
+; RV32-NEXT:    lui a2, 4080
+; RV32-NEXT:    mvm a0, a1, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_insert_vector_8_elem2:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srli a2, a0, 8
-; CHECK-RV64-NEXT:    srli a3, a0, 24
-; CHECK-RV64-NEXT:    ppaire.b a1, a1, a3
-; CHECK-RV64-NEXT:    ppaire.b a0, a0, a2
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_insert_vector_8_elem2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srli a2, a0, 8
+; RV64-NEXT:    srli a3, a0, 24
+; RV64-NEXT:    ppaire.b a1, a1, a3
+; RV64-NEXT:    ppaire.b a0, a0, a2
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = insertelement <4 x i8> %a, i8 %val, i32 2
   ret <4 x i8> %res
 }
@@ -687,18 +687,18 @@ define <2 x i16> @test_padd_hs_splat_rhs(<2 x i16> %a, i16 %b) {
 }
 
 define <4 x i8> @test_build_vector_i8(i8 %a, i8 %c, i8 %b, i8 %d) {
-; CHECK-RV32-LABEL: test_build_vector_i8:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    ppaire.db a0, a0, a2
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_build_vector_i8:
+; RV32:       # %bb.0:
+; RV32-NEXT:    ppaire.db a0, a0, a2
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_build_vector_i8:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    ppaire.b a1, a1, a3
-; CHECK-RV64-NEXT:    ppaire.b a0, a0, a2
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_build_vector_i8:
+; RV64:       # %bb.0:
+; RV64-NEXT:    ppaire.b a1, a1, a3
+; RV64-NEXT:    ppaire.b a0, a0, a2
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %v0 = insertelement <4 x i8> poison, i8 %a, i32 0
   %v1 = insertelement <4 x i8> %v0, i8 %b, i32 1
   %v2 = insertelement <4 x i8> %v1, i8 %c, i32 2
@@ -707,15 +707,15 @@ define <4 x i8> @test_build_vector_i8(i8 %a, i8 %c, i8 %b, i8 %d) {
 }
 
 define <2 x i16> @test_build_vector_i16(i16 %a, i16 %b) {
-; CHECK-RV32-LABEL: test_build_vector_i16:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_build_vector_i16:
+; RV32:       # %bb.0:
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_build_vector_i16:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_build_vector_i16:
+; RV64:       # %bb.0:
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %v0 = insertelement <2 x i16> poison, i16 %a, i32 0
   %v1 = insertelement <2 x i16> %v0, i16 %b, i32 1
   ret <2 x i16> %v1
@@ -791,63 +791,63 @@ define <2 x i16> @test_pssla_hs(<2 x i16> %a, i16 %shamt) {
 
 ; Test saturating shift left arithmetic with non-splat shift amount for v2i16
 define <2 x i16> @test_pssla_h(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_pssla_h:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    sll a2, a0, a1
-; CHECK-RV32-NEXT:    srli a3, a1, 16
-; CHECK-RV32-NEXT:    srli a4, a0, 16
-; CHECK-RV32-NEXT:    sext.h a5, a2
-; CHECK-RV32-NEXT:    sra a1, a5, a1
-; CHECK-RV32-NEXT:    pmsltz.h a5, a0
-; CHECK-RV32-NEXT:    sll a4, a4, a3
-; CHECK-RV32-NEXT:    pack a2, a2, a4
-; CHECK-RV32-NEXT:    sext.h a4, a4
-; CHECK-RV32-NEXT:    sra a3, a4, a3
-; CHECK-RV32-NEXT:    lui a4, 8
-; CHECK-RV32-NEXT:    pack a1, a1, a3
-; CHECK-RV32-NEXT:    plui.h a3, -512
-; CHECK-RV32-NEXT:    addi a4, a4, -1
-; CHECK-RV32-NEXT:    pmv.hs a4, a4
-; CHECK-RV32-NEXT:    pmseq.h a0, a0, a1
-; CHECK-RV32-NEXT:    merge a5, a4, a3
-; CHECK-RV32-NEXT:    merge a0, a5, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_pssla_h:
+; RV32:       # %bb.0:
+; RV32-NEXT:    sll a2, a0, a1
+; RV32-NEXT:    srli a3, a1, 16
+; RV32-NEXT:    srli a4, a0, 16
+; RV32-NEXT:    sext.h a5, a2
+; RV32-NEXT:    sra a1, a5, a1
+; RV32-NEXT:    pmsltz.h a5, a0
+; RV32-NEXT:    sll a4, a4, a3
+; RV32-NEXT:    pack a2, a2, a4
+; RV32-NEXT:    sext.h a4, a4
+; RV32-NEXT:    sra a3, a4, a3
+; RV32-NEXT:    lui a4, 8
+; RV32-NEXT:    pack a1, a1, a3
+; RV32-NEXT:    plui.h a3, -512
+; RV32-NEXT:    addi a4, a4, -1
+; RV32-NEXT:    pmv.hs a4, a4
+; RV32-NEXT:    pmseq.h a0, a0, a1
+; RV32-NEXT:    merge a5, a4, a3
+; RV32-NEXT:    merge a0, a5, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_pssla_h:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srli a2, a1, 48
-; CHECK-RV64-NEXT:    srli a3, a0, 48
-; CHECK-RV64-NEXT:    srli a4, a1, 32
-; CHECK-RV64-NEXT:    srli a5, a0, 32
-; CHECK-RV64-NEXT:    sll a6, a0, a1
-; CHECK-RV64-NEXT:    srli a7, a1, 16
-; CHECK-RV64-NEXT:    srli t0, a0, 16
-; CHECK-RV64-NEXT:    pmsltz.h t1, a0
-; CHECK-RV64-NEXT:    sll a3, a3, a2
-; CHECK-RV64-NEXT:    sll a5, a5, a4
-; CHECK-RV64-NEXT:    sll t0, t0, a7
-; CHECK-RV64-NEXT:    sext.h t2, a6
-; CHECK-RV64-NEXT:    sra a1, t2, a1
-; CHECK-RV64-NEXT:    ppaire.h t2, a5, a3
-; CHECK-RV64-NEXT:    ppaire.h a6, a6, t0
-; CHECK-RV64-NEXT:    pack a6, a6, t2
-; CHECK-RV64-NEXT:    lui t2, 8
-; CHECK-RV64-NEXT:    sext.h a3, a3
-; CHECK-RV64-NEXT:    sra a2, a3, a2
-; CHECK-RV64-NEXT:    plui.h a3, -512
-; CHECK-RV64-NEXT:    addi t2, t2, -1
-; CHECK-RV64-NEXT:    sext.h a5, a5
-; CHECK-RV64-NEXT:    sext.h t0, t0
-; CHECK-RV64-NEXT:    pmv.hs t2, t2
-; CHECK-RV64-NEXT:    sra a4, a5, a4
-; CHECK-RV64-NEXT:    sra a5, t0, a7
-; CHECK-RV64-NEXT:    ppaire.h a2, a4, a2
-; CHECK-RV64-NEXT:    ppaire.h a1, a1, a5
-; CHECK-RV64-NEXT:    pack a1, a1, a2
-; CHECK-RV64-NEXT:    pmseq.h a0, a0, a1
-; CHECK-RV64-NEXT:    merge t1, t2, a3
-; CHECK-RV64-NEXT:    merge a0, t1, a6
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_pssla_h:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srli a2, a1, 48
+; RV64-NEXT:    srli a3, a0, 48
+; RV64-NEXT:    srli a4, a1, 32
+; RV64-NEXT:    srli a5, a0, 32
+; RV64-NEXT:    sll a6, a0, a1
+; RV64-NEXT:    srli a7, a1, 16
+; RV64-NEXT:    srli t0, a0, 16
+; RV64-NEXT:    pmsltz.h t1, a0
+; RV64-NEXT:    sll a3, a3, a2
+; RV64-NEXT:    sll a5, a5, a4
+; RV64-NEXT:    sll t0, t0, a7
+; RV64-NEXT:    sext.h t2, a6
+; RV64-NEXT:    sra a1, t2, a1
+; RV64-NEXT:    ppaire.h t2, a5, a3
+; RV64-NEXT:    ppaire.h a6, a6, t0
+; RV64-NEXT:    pack a6, a6, t2
+; RV64-NEXT:    lui t2, 8
+; RV64-NEXT:    sext.h a3, a3
+; RV64-NEXT:    sra a2, a3, a2
+; RV64-NEXT:    plui.h a3, -512
+; RV64-NEXT:    addi t2, t2, -1
+; RV64-NEXT:    sext.h a5, a5
+; RV64-NEXT:    sext.h t0, t0
+; RV64-NEXT:    pmv.hs t2, t2
+; RV64-NEXT:    sra a4, a5, a4
+; RV64-NEXT:    sra a5, t0, a7
+; RV64-NEXT:    ppaire.h a2, a4, a2
+; RV64-NEXT:    ppaire.h a1, a1, a5
+; RV64-NEXT:    pack a1, a1, a2
+; RV64-NEXT:    pmseq.h a0, a0, a1
+; RV64-NEXT:    merge t1, t2, a3
+; RV64-NEXT:    merge a0, t1, a6
+; RV64-NEXT:    ret
   %res = call <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16> %a, <2 x i16> %b)
   ret <2 x i16> %res
 }
@@ -939,60 +939,60 @@ define <4 x i8> @test_psll_bs_mask(<4 x i8> %a, i8 %shamt) {
 
 ; Test logical shift left(vector shamt)
 define <2 x i16> @test_psll_hs_vec_shamt(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_psll_hs_vec_shamt:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    sll a2, a0, a1
-; CHECK-RV32-NEXT:    srli a1, a1, 16
-; CHECK-RV32-NEXT:    srli a0, a0, 16
-; CHECK-RV32-NEXT:    sll a0, a0, a1
-; CHECK-RV32-NEXT:    pack a0, a2, a0
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psll_hs_vec_shamt:
+; RV32:       # %bb.0:
+; RV32-NEXT:    sll a2, a0, a1
+; RV32-NEXT:    srli a1, a1, 16
+; RV32-NEXT:    srli a0, a0, 16
+; RV32-NEXT:    sll a0, a0, a1
+; RV32-NEXT:    pack a0, a2, a0
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psll_hs_vec_shamt:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    sll a2, a0, a1
-; CHECK-RV64-NEXT:    srli a1, a1, 16
-; CHECK-RV64-NEXT:    srli a0, a0, 16
-; CHECK-RV64-NEXT:    sll a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.h a0, a2, a0
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psll_hs_vec_shamt:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sll a2, a0, a1
+; RV64-NEXT:    srli a1, a1, 16
+; RV64-NEXT:    srli a0, a0, 16
+; RV64-NEXT:    sll a0, a0, a1
+; RV64-NEXT:    ppaire.h a0, a2, a0
+; RV64-NEXT:    ret
   %res = shl <2 x i16> %a, %b
   ret <2 x i16> %res
 }
 
 define <4 x i8> @test_psll_bs_vec_shamt(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-RV32-LABEL: test_psll_bs_vec_shamt:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 24
-; CHECK-RV32-NEXT:    srli a3, a0, 24
-; CHECK-RV32-NEXT:    srli a4, a1, 8
-; CHECK-RV32-NEXT:    srli a5, a0, 8
-; CHECK-RV32-NEXT:    sll a3, a3, a2
-; CHECK-RV32-NEXT:    sll a2, a5, a4
-; CHECK-RV32-NEXT:    sll a4, a0, a1
-; CHECK-RV32-NEXT:    srli a1, a1, 16
-; CHECK-RV32-NEXT:    srli a0, a0, 16
-; CHECK-RV32-NEXT:    sll a5, a0, a1
-; CHECK-RV32-NEXT:    ppaire.db a0, a4, a2
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psll_bs_vec_shamt:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 24
+; RV32-NEXT:    srli a3, a0, 24
+; RV32-NEXT:    srli a4, a1, 8
+; RV32-NEXT:    srli a5, a0, 8
+; RV32-NEXT:    sll a3, a3, a2
+; RV32-NEXT:    sll a2, a5, a4
+; RV32-NEXT:    sll a4, a0, a1
+; RV32-NEXT:    srli a1, a1, 16
+; RV32-NEXT:    srli a0, a0, 16
+; RV32-NEXT:    sll a5, a0, a1
+; RV32-NEXT:    ppaire.db a0, a4, a2
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psll_bs_vec_shamt:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srli a2, a1, 24
-; CHECK-RV64-NEXT:    srli a3, a0, 24
-; CHECK-RV64-NEXT:    srli a4, a1, 16
-; CHECK-RV64-NEXT:    sll a2, a3, a2
-; CHECK-RV64-NEXT:    srli a3, a0, 16
-; CHECK-RV64-NEXT:    sll a3, a3, a4
-; CHECK-RV64-NEXT:    sll a4, a0, a1
-; CHECK-RV64-NEXT:    srli a1, a1, 8
-; CHECK-RV64-NEXT:    srli a0, a0, 8
-; CHECK-RV64-NEXT:    sll a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.b a1, a3, a2
-; CHECK-RV64-NEXT:    ppaire.b a0, a4, a0
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psll_bs_vec_shamt:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srli a2, a1, 24
+; RV64-NEXT:    srli a3, a0, 24
+; RV64-NEXT:    srli a4, a1, 16
+; RV64-NEXT:    sll a2, a3, a2
+; RV64-NEXT:    srli a3, a0, 16
+; RV64-NEXT:    sll a3, a3, a4
+; RV64-NEXT:    sll a4, a0, a1
+; RV64-NEXT:    srli a1, a1, 8
+; RV64-NEXT:    srli a0, a0, 8
+; RV64-NEXT:    sll a0, a0, a1
+; RV64-NEXT:    ppaire.b a1, a3, a2
+; RV64-NEXT:    ppaire.b a0, a4, a0
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = shl <4 x i8> %a, %b
   ret <4 x i8> %res
 }
@@ -1093,138 +1093,138 @@ define <4 x i8> @test_psra_bs_mask(<4 x i8> %a, i8 %shamt) {
 
 ; Test logical shift right(vector shamt)
 define <2 x i16> @test_psrl_hs_vec_shamt(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_psrl_hs_vec_shamt:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 16
-; CHECK-RV32-NEXT:    srli a3, a0, 16
-; CHECK-RV32-NEXT:    zext.h a0, a0
-; CHECK-RV32-NEXT:    srl a2, a3, a2
-; CHECK-RV32-NEXT:    srl a0, a0, a1
-; CHECK-RV32-NEXT:    pack a0, a0, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psrl_hs_vec_shamt:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 16
+; RV32-NEXT:    srli a3, a0, 16
+; RV32-NEXT:    zext.h a0, a0
+; RV32-NEXT:    srl a2, a3, a2
+; RV32-NEXT:    srl a0, a0, a1
+; RV32-NEXT:    pack a0, a0, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psrl_hs_vec_shamt:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srli a2, a1, 16
-; CHECK-RV64-NEXT:    srliw a3, a0, 16
-; CHECK-RV64-NEXT:    zext.h a0, a0
-; CHECK-RV64-NEXT:    srl a2, a3, a2
-; CHECK-RV64-NEXT:    srl a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a2
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psrl_hs_vec_shamt:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srli a2, a1, 16
+; RV64-NEXT:    srliw a3, a0, 16
+; RV64-NEXT:    zext.h a0, a0
+; RV64-NEXT:    srl a2, a3, a2
+; RV64-NEXT:    srl a0, a0, a1
+; RV64-NEXT:    ppaire.h a0, a0, a2
+; RV64-NEXT:    ret
   %res = lshr <2 x i16> %a, %b
   ret <2 x i16> %res
 }
 
 define <4 x i8> @test_psrl_bs_vec_shamt(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-RV32-LABEL: test_psrl_bs_vec_shamt:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 24
-; CHECK-RV32-NEXT:    srli a3, a0, 24
-; CHECK-RV32-NEXT:    srli a4, a1, 8
-; CHECK-RV32-NEXT:    slli a5, a0, 16
-; CHECK-RV32-NEXT:    srl a3, a3, a2
-; CHECK-RV32-NEXT:    srli a5, a5, 24
-; CHECK-RV32-NEXT:    srl a2, a5, a4
-; CHECK-RV32-NEXT:    zext.b a4, a0
-; CHECK-RV32-NEXT:    srli a5, a1, 16
-; CHECK-RV32-NEXT:    slli a0, a0, 8
-; CHECK-RV32-NEXT:    srl a4, a4, a1
-; CHECK-RV32-NEXT:    srli a0, a0, 24
-; CHECK-RV32-NEXT:    srl a5, a0, a5
-; CHECK-RV32-NEXT:    ppaire.db a0, a4, a2
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psrl_bs_vec_shamt:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 24
+; RV32-NEXT:    srli a3, a0, 24
+; RV32-NEXT:    srli a4, a1, 8
+; RV32-NEXT:    slli a5, a0, 16
+; RV32-NEXT:    srl a3, a3, a2
+; RV32-NEXT:    srli a5, a5, 24
+; RV32-NEXT:    srl a2, a5, a4
+; RV32-NEXT:    zext.b a4, a0
+; RV32-NEXT:    srli a5, a1, 16
+; RV32-NEXT:    slli a0, a0, 8
+; RV32-NEXT:    srl a4, a4, a1
+; RV32-NEXT:    srli a0, a0, 24
+; RV32-NEXT:    srl a5, a0, a5
+; RV32-NEXT:    ppaire.db a0, a4, a2
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psrl_bs_vec_shamt:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srli a2, a1, 24
-; CHECK-RV64-NEXT:    srliw a3, a0, 24
-; CHECK-RV64-NEXT:    srli a4, a1, 16
-; CHECK-RV64-NEXT:    srl a2, a3, a2
-; CHECK-RV64-NEXT:    slli a3, a0, 40
-; CHECK-RV64-NEXT:    srli a3, a3, 56
-; CHECK-RV64-NEXT:    srl a3, a3, a4
-; CHECK-RV64-NEXT:    zext.b a4, a0
-; CHECK-RV64-NEXT:    srl a4, a4, a1
-; CHECK-RV64-NEXT:    srli a1, a1, 8
-; CHECK-RV64-NEXT:    slli a0, a0, 48
-; CHECK-RV64-NEXT:    srli a0, a0, 56
-; CHECK-RV64-NEXT:    srl a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.b a1, a3, a2
-; CHECK-RV64-NEXT:    ppaire.b a0, a4, a0
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psrl_bs_vec_shamt:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srli a2, a1, 24
+; RV64-NEXT:    srliw a3, a0, 24
+; RV64-NEXT:    srli a4, a1, 16
+; RV64-NEXT:    srl a2, a3, a2
+; RV64-NEXT:    slli a3, a0, 40
+; RV64-NEXT:    srli a3, a3, 56
+; RV64-NEXT:    srl a3, a3, a4
+; RV64-NEXT:    zext.b a4, a0
+; RV64-NEXT:    srl a4, a4, a1
+; RV64-NEXT:    srli a1, a1, 8
+; RV64-NEXT:    slli a0, a0, 48
+; RV64-NEXT:    srli a0, a0, 56
+; RV64-NEXT:    srl a0, a0, a1
+; RV64-NEXT:    ppaire.b a1, a3, a2
+; RV64-NEXT:    ppaire.b a0, a4, a0
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = lshr <4 x i8> %a, %b
   ret <4 x i8> %res
 }
 
 ; Test arithmetic shift right(vector shamt)
 define <2 x i16> @test_psra_hs_vec_shamt(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_psra_hs_vec_shamt:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 16
-; CHECK-RV32-NEXT:    srai a3, a0, 16
-; CHECK-RV32-NEXT:    sext.h a0, a0
-; CHECK-RV32-NEXT:    sra a2, a3, a2
-; CHECK-RV32-NEXT:    sra a0, a0, a1
-; CHECK-RV32-NEXT:    pack a0, a0, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psra_hs_vec_shamt:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 16
+; RV32-NEXT:    srai a3, a0, 16
+; RV32-NEXT:    sext.h a0, a0
+; RV32-NEXT:    sra a2, a3, a2
+; RV32-NEXT:    sra a0, a0, a1
+; RV32-NEXT:    pack a0, a0, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psra_hs_vec_shamt:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    sext.h a2, a0
-; CHECK-RV64-NEXT:    sra a2, a2, a1
-; CHECK-RV64-NEXT:    srli a1, a1, 16
-; CHECK-RV64-NEXT:    slli a0, a0, 32
-; CHECK-RV64-NEXT:    srai a0, a0, 48
-; CHECK-RV64-NEXT:    sra a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.h a0, a2, a0
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psra_hs_vec_shamt:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.h a2, a0
+; RV64-NEXT:    sra a2, a2, a1
+; RV64-NEXT:    srli a1, a1, 16
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srai a0, a0, 48
+; RV64-NEXT:    sra a0, a0, a1
+; RV64-NEXT:    ppaire.h a0, a2, a0
+; RV64-NEXT:    ret
   %res = ashr <2 x i16> %a, %b
   ret <2 x i16> %res
 }
 
 define <4 x i8> @test_psra_bs_vec_shamt(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-RV32-LABEL: test_psra_bs_vec_shamt:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 24
-; CHECK-RV32-NEXT:    srai a3, a0, 24
-; CHECK-RV32-NEXT:    srli a4, a1, 8
-; CHECK-RV32-NEXT:    slli a5, a0, 16
-; CHECK-RV32-NEXT:    sra a3, a3, a2
-; CHECK-RV32-NEXT:    srai a5, a5, 24
-; CHECK-RV32-NEXT:    sra a2, a5, a4
-; CHECK-RV32-NEXT:    sext.b a4, a0
-; CHECK-RV32-NEXT:    srli a5, a1, 16
-; CHECK-RV32-NEXT:    slli a0, a0, 8
-; CHECK-RV32-NEXT:    sra a4, a4, a1
-; CHECK-RV32-NEXT:    srai a0, a0, 24
-; CHECK-RV32-NEXT:    sra a5, a0, a5
-; CHECK-RV32-NEXT:    ppaire.db a0, a4, a2
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psra_bs_vec_shamt:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 24
+; RV32-NEXT:    srai a3, a0, 24
+; RV32-NEXT:    srli a4, a1, 8
+; RV32-NEXT:    slli a5, a0, 16
+; RV32-NEXT:    sra a3, a3, a2
+; RV32-NEXT:    srai a5, a5, 24
+; RV32-NEXT:    sra a2, a5, a4
+; RV32-NEXT:    sext.b a4, a0
+; RV32-NEXT:    srli a5, a1, 16
+; RV32-NEXT:    slli a0, a0, 8
+; RV32-NEXT:    sra a4, a4, a1
+; RV32-NEXT:    srai a0, a0, 24
+; RV32-NEXT:    sra a5, a0, a5
+; RV32-NEXT:    ppaire.db a0, a4, a2
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psra_bs_vec_shamt:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srli a2, a1, 24
-; CHECK-RV64-NEXT:    slli a3, a0, 32
-; CHECK-RV64-NEXT:    srli a4, a1, 16
-; CHECK-RV64-NEXT:    srai a3, a3, 56
-; CHECK-RV64-NEXT:    sra a2, a3, a2
-; CHECK-RV64-NEXT:    slli a3, a0, 40
-; CHECK-RV64-NEXT:    srai a3, a3, 56
-; CHECK-RV64-NEXT:    sra a3, a3, a4
-; CHECK-RV64-NEXT:    sext.b a4, a0
-; CHECK-RV64-NEXT:    sra a4, a4, a1
-; CHECK-RV64-NEXT:    srli a1, a1, 8
-; CHECK-RV64-NEXT:    slli a0, a0, 48
-; CHECK-RV64-NEXT:    srai a0, a0, 56
-; CHECK-RV64-NEXT:    sra a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.b a1, a3, a2
-; CHECK-RV64-NEXT:    ppaire.b a0, a4, a0
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psra_bs_vec_shamt:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srli a2, a1, 24
+; RV64-NEXT:    slli a3, a0, 32
+; RV64-NEXT:    srli a4, a1, 16
+; RV64-NEXT:    srai a3, a3, 56
+; RV64-NEXT:    sra a2, a3, a2
+; RV64-NEXT:    slli a3, a0, 40
+; RV64-NEXT:    srai a3, a3, 56
+; RV64-NEXT:    sra a3, a3, a4
+; RV64-NEXT:    sext.b a4, a0
+; RV64-NEXT:    sra a4, a4, a1
+; RV64-NEXT:    srli a1, a1, 8
+; RV64-NEXT:    slli a0, a0, 48
+; RV64-NEXT:    srai a0, a0, 56
+; RV64-NEXT:    sra a0, a0, a1
+; RV64-NEXT:    ppaire.b a1, a3, a2
+; RV64-NEXT:    ppaire.b a0, a4, a0
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = ashr <4 x i8> %a, %b
   ret <4 x i8> %res
 }
@@ -1345,345 +1345,345 @@ define <2 x i16> @test_pmulhrsu_h_commuted(<2 x i16> %a, <2 x i16> %b) {
 
 ; Test packed multiply low for v2i16
 define <2 x i16> @test_pmul_h(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_pmul_h:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    pwmul.h a0, a0, a1
-; CHECK-RV32-NEXT:    pncvt.h a0, a0
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_pmul_h:
+; RV32:       # %bb.0:
+; RV32-NEXT:    pwmul.h a0, a0, a1
+; RV32-NEXT:    pncvt.h a0, a0
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_pmul_h:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    pmul.w.h11 a2, a0, a1
-; CHECK-RV64-NEXT:    pmul.w.h00 a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a2
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_pmul_h:
+; RV64:       # %bb.0:
+; RV64-NEXT:    pmul.w.h11 a2, a0, a1
+; RV64-NEXT:    pmul.w.h00 a0, a0, a1
+; RV64-NEXT:    ppaire.h a0, a0, a2
+; RV64-NEXT:    ret
   %res = mul <2 x i16> %a, %b
   ret <2 x i16> %res
 }
 
 ; Test packed multiply low for v4i8
 define <4 x i8> @test_pmul_b(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-RV32-LABEL: test_pmul_b:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    pwmul.b a0, a0, a1
-; CHECK-RV32-NEXT:    pncvt.b a0, a0
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_pmul_b:
+; RV32:       # %bb.0:
+; RV32-NEXT:    pwmul.b a0, a0, a1
+; RV32-NEXT:    pncvt.b a0, a0
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_pmul_b:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    pmul.h.b11 a2, a0, a1
-; CHECK-RV64-NEXT:    pmul.h.b00 a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.b a0, a0, a2
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_pmul_b:
+; RV64:       # %bb.0:
+; RV64-NEXT:    pmul.h.b11 a2, a0, a1
+; RV64-NEXT:    pmul.h.b00 a0, a0, a1
+; RV64-NEXT:    ppaire.b a0, a0, a2
+; RV64-NEXT:    ret
   %res = mul <4 x i8> %a, %b
   ret <4 x i8> %res
 }
 
 ; Division and remainder tests
 define <2 x i16> @test_psdiv_h(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_psdiv_h:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srai a2, a1, 16
-; CHECK-RV32-NEXT:    srai a3, a0, 16
-; CHECK-RV32-NEXT:    sext.h a1, a1
-; CHECK-RV32-NEXT:    sext.h a0, a0
-; CHECK-RV32-NEXT:    div a2, a3, a2
-; CHECK-RV32-NEXT:    div a0, a0, a1
-; CHECK-RV32-NEXT:    pack a0, a0, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psdiv_h:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srai a2, a1, 16
+; RV32-NEXT:    srai a3, a0, 16
+; RV32-NEXT:    sext.h a1, a1
+; RV32-NEXT:    sext.h a0, a0
+; RV32-NEXT:    div a2, a3, a2
+; RV32-NEXT:    div a0, a0, a1
+; RV32-NEXT:    pack a0, a0, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psdiv_h:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    sext.h a2, a1
-; CHECK-RV64-NEXT:    sext.h a3, a0
-; CHECK-RV64-NEXT:    slli a1, a1, 32
-; CHECK-RV64-NEXT:    slli a0, a0, 32
-; CHECK-RV64-NEXT:    divw a2, a3, a2
-; CHECK-RV64-NEXT:    srai a1, a1, 48
-; CHECK-RV64-NEXT:    srai a0, a0, 48
-; CHECK-RV64-NEXT:    divw a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.h a0, a2, a0
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psdiv_h:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.h a2, a1
+; RV64-NEXT:    sext.h a3, a0
+; RV64-NEXT:    slli a1, a1, 32
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    divw a2, a3, a2
+; RV64-NEXT:    srai a1, a1, 48
+; RV64-NEXT:    srai a0, a0, 48
+; RV64-NEXT:    divw a0, a0, a1
+; RV64-NEXT:    ppaire.h a0, a2, a0
+; RV64-NEXT:    ret
   %res = sdiv <2 x i16> %a, %b
   ret <2 x i16> %res
 }
 
 define <4 x i8> @test_psdiv_b(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-RV32-LABEL: test_psdiv_b:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srai a2, a1, 24
-; CHECK-RV32-NEXT:    srai a3, a0, 24
-; CHECK-RV32-NEXT:    slli a4, a1, 16
-; CHECK-RV32-NEXT:    slli a5, a0, 16
-; CHECK-RV32-NEXT:    div a3, a3, a2
-; CHECK-RV32-NEXT:    srai a4, a4, 24
-; CHECK-RV32-NEXT:    srai a5, a5, 24
-; CHECK-RV32-NEXT:    div a2, a5, a4
-; CHECK-RV32-NEXT:    sext.b a4, a1
-; CHECK-RV32-NEXT:    sext.b a5, a0
-; CHECK-RV32-NEXT:    slli a1, a1, 8
-; CHECK-RV32-NEXT:    slli a0, a0, 8
-; CHECK-RV32-NEXT:    div a4, a5, a4
-; CHECK-RV32-NEXT:    srai a1, a1, 24
-; CHECK-RV32-NEXT:    srai a0, a0, 24
-; CHECK-RV32-NEXT:    div a5, a0, a1
-; CHECK-RV32-NEXT:    ppaire.db a0, a4, a2
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psdiv_b:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srai a2, a1, 24
+; RV32-NEXT:    srai a3, a0, 24
+; RV32-NEXT:    slli a4, a1, 16
+; RV32-NEXT:    slli a5, a0, 16
+; RV32-NEXT:    div a3, a3, a2
+; RV32-NEXT:    srai a4, a4, 24
+; RV32-NEXT:    srai a5, a5, 24
+; RV32-NEXT:    div a2, a5, a4
+; RV32-NEXT:    sext.b a4, a1
+; RV32-NEXT:    sext.b a5, a0
+; RV32-NEXT:    slli a1, a1, 8
+; RV32-NEXT:    slli a0, a0, 8
+; RV32-NEXT:    div a4, a5, a4
+; RV32-NEXT:    srai a1, a1, 24
+; RV32-NEXT:    srai a0, a0, 24
+; RV32-NEXT:    div a5, a0, a1
+; RV32-NEXT:    ppaire.db a0, a4, a2
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psdiv_b:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    slli a2, a1, 32
-; CHECK-RV64-NEXT:    slli a3, a0, 32
-; CHECK-RV64-NEXT:    sext.b a4, a1
-; CHECK-RV64-NEXT:    sext.b a5, a0
-; CHECK-RV64-NEXT:    divw a4, a5, a4
-; CHECK-RV64-NEXT:    slli a5, a1, 40
-; CHECK-RV64-NEXT:    srai a2, a2, 56
-; CHECK-RV64-NEXT:    srai a3, a3, 56
-; CHECK-RV64-NEXT:    divw a2, a3, a2
-; CHECK-RV64-NEXT:    slli a3, a0, 40
-; CHECK-RV64-NEXT:    srai a5, a5, 56
-; CHECK-RV64-NEXT:    srai a3, a3, 56
-; CHECK-RV64-NEXT:    divw a3, a3, a5
-; CHECK-RV64-NEXT:    slli a1, a1, 48
-; CHECK-RV64-NEXT:    slli a0, a0, 48
-; CHECK-RV64-NEXT:    srai a1, a1, 56
-; CHECK-RV64-NEXT:    srai a0, a0, 56
-; CHECK-RV64-NEXT:    divw a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.b a1, a3, a2
-; CHECK-RV64-NEXT:    ppaire.b a0, a4, a0
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psdiv_b:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a2, a1, 32
+; RV64-NEXT:    slli a3, a0, 32
+; RV64-NEXT:    sext.b a4, a1
+; RV64-NEXT:    sext.b a5, a0
+; RV64-NEXT:    divw a4, a5, a4
+; RV64-NEXT:    slli a5, a1, 40
+; RV64-NEXT:    srai a2, a2, 56
+; RV64-NEXT:    srai a3, a3, 56
+; RV64-NEXT:    divw a2, a3, a2
+; RV64-NEXT:    slli a3, a0, 40
+; RV64-NEXT:    srai a5, a5, 56
+; RV64-NEXT:    srai a3, a3, 56
+; RV64-NEXT:    divw a3, a3, a5
+; RV64-NEXT:    slli a1, a1, 48
+; RV64-NEXT:    slli a0, a0, 48
+; RV64-NEXT:    srai a1, a1, 56
+; RV64-NEXT:    srai a0, a0, 56
+; RV64-NEXT:    divw a0, a0, a1
+; RV64-NEXT:    ppaire.b a1, a3, a2
+; RV64-NEXT:    ppaire.b a0, a4, a0
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = sdiv <4 x i8> %a, %b
   ret <4 x i8> %res
 }
 
 define <2 x i16> @test_pudiv_h(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_pudiv_h:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 16
-; CHECK-RV32-NEXT:    srli a3, a0, 16
-; CHECK-RV32-NEXT:    zext.h a1, a1
-; CHECK-RV32-NEXT:    zext.h a0, a0
-; CHECK-RV32-NEXT:    divu a2, a3, a2
-; CHECK-RV32-NEXT:    divu a0, a0, a1
-; CHECK-RV32-NEXT:    pack a0, a0, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_pudiv_h:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 16
+; RV32-NEXT:    srli a3, a0, 16
+; RV32-NEXT:    zext.h a1, a1
+; RV32-NEXT:    zext.h a0, a0
+; RV32-NEXT:    divu a2, a3, a2
+; RV32-NEXT:    divu a0, a0, a1
+; RV32-NEXT:    pack a0, a0, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_pudiv_h:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srliw a2, a1, 16
-; CHECK-RV64-NEXT:    srliw a3, a0, 16
-; CHECK-RV64-NEXT:    zext.h a1, a1
-; CHECK-RV64-NEXT:    zext.h a0, a0
-; CHECK-RV64-NEXT:    divuw a2, a3, a2
-; CHECK-RV64-NEXT:    divuw a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a2
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_pudiv_h:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srliw a2, a1, 16
+; RV64-NEXT:    srliw a3, a0, 16
+; RV64-NEXT:    zext.h a1, a1
+; RV64-NEXT:    zext.h a0, a0
+; RV64-NEXT:    divuw a2, a3, a2
+; RV64-NEXT:    divuw a0, a0, a1
+; RV64-NEXT:    ppaire.h a0, a0, a2
+; RV64-NEXT:    ret
   %res = udiv <2 x i16> %a, %b
   ret <2 x i16> %res
 }
 
 define <4 x i8> @test_pudiv_b(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-RV32-LABEL: test_pudiv_b:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 24
-; CHECK-RV32-NEXT:    srli a3, a0, 24
-; CHECK-RV32-NEXT:    slli a4, a1, 16
-; CHECK-RV32-NEXT:    slli a5, a0, 16
-; CHECK-RV32-NEXT:    divu a3, a3, a2
-; CHECK-RV32-NEXT:    srli a4, a4, 24
-; CHECK-RV32-NEXT:    srli a5, a5, 24
-; CHECK-RV32-NEXT:    divu a2, a5, a4
-; CHECK-RV32-NEXT:    zext.b a4, a1
-; CHECK-RV32-NEXT:    zext.b a5, a0
-; CHECK-RV32-NEXT:    slli a1, a1, 8
-; CHECK-RV32-NEXT:    slli a0, a0, 8
-; CHECK-RV32-NEXT:    divu a4, a5, a4
-; CHECK-RV32-NEXT:    srli a1, a1, 24
-; CHECK-RV32-NEXT:    srli a0, a0, 24
-; CHECK-RV32-NEXT:    divu a5, a0, a1
-; CHECK-RV32-NEXT:    ppaire.db a0, a4, a2
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_pudiv_b:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 24
+; RV32-NEXT:    srli a3, a0, 24
+; RV32-NEXT:    slli a4, a1, 16
+; RV32-NEXT:    slli a5, a0, 16
+; RV32-NEXT:    divu a3, a3, a2
+; RV32-NEXT:    srli a4, a4, 24
+; RV32-NEXT:    srli a5, a5, 24
+; RV32-NEXT:    divu a2, a5, a4
+; RV32-NEXT:    zext.b a4, a1
+; RV32-NEXT:    zext.b a5, a0
+; RV32-NEXT:    slli a1, a1, 8
+; RV32-NEXT:    slli a0, a0, 8
+; RV32-NEXT:    divu a4, a5, a4
+; RV32-NEXT:    srli a1, a1, 24
+; RV32-NEXT:    srli a0, a0, 24
+; RV32-NEXT:    divu a5, a0, a1
+; RV32-NEXT:    ppaire.db a0, a4, a2
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_pudiv_b:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srliw a2, a1, 24
-; CHECK-RV64-NEXT:    srliw a3, a0, 24
-; CHECK-RV64-NEXT:    slli a4, a1, 40
-; CHECK-RV64-NEXT:    zext.b a5, a1
-; CHECK-RV64-NEXT:    divuw a2, a3, a2
-; CHECK-RV64-NEXT:    zext.b a3, a0
-; CHECK-RV64-NEXT:    divuw a3, a3, a5
-; CHECK-RV64-NEXT:    slli a5, a0, 40
-; CHECK-RV64-NEXT:    srli a4, a4, 56
-; CHECK-RV64-NEXT:    srli a5, a5, 56
-; CHECK-RV64-NEXT:    divuw a4, a5, a4
-; CHECK-RV64-NEXT:    slli a1, a1, 48
-; CHECK-RV64-NEXT:    slli a0, a0, 48
-; CHECK-RV64-NEXT:    srli a1, a1, 56
-; CHECK-RV64-NEXT:    srli a0, a0, 56
-; CHECK-RV64-NEXT:    divuw a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.b a1, a4, a2
-; CHECK-RV64-NEXT:    ppaire.b a0, a3, a0
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_pudiv_b:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srliw a2, a1, 24
+; RV64-NEXT:    srliw a3, a0, 24
+; RV64-NEXT:    slli a4, a1, 40
+; RV64-NEXT:    zext.b a5, a1
+; RV64-NEXT:    divuw a2, a3, a2
+; RV64-NEXT:    zext.b a3, a0
+; RV64-NEXT:    divuw a3, a3, a5
+; RV64-NEXT:    slli a5, a0, 40
+; RV64-NEXT:    srli a4, a4, 56
+; RV64-NEXT:    srli a5, a5, 56
+; RV64-NEXT:    divuw a4, a5, a4
+; RV64-NEXT:    slli a1, a1, 48
+; RV64-NEXT:    slli a0, a0, 48
+; RV64-NEXT:    srli a1, a1, 56
+; RV64-NEXT:    srli a0, a0, 56
+; RV64-NEXT:    divuw a0, a0, a1
+; RV64-NEXT:    ppaire.b a1, a4, a2
+; RV64-NEXT:    ppaire.b a0, a3, a0
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = udiv <4 x i8> %a, %b
   ret <4 x i8> %res
 }
 
 define <2 x i16> @test_psrem_h(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_psrem_h:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srai a2, a1, 16
-; CHECK-RV32-NEXT:    srai a3, a0, 16
-; CHECK-RV32-NEXT:    sext.h a1, a1
-; CHECK-RV32-NEXT:    sext.h a0, a0
-; CHECK-RV32-NEXT:    rem a2, a3, a2
-; CHECK-RV32-NEXT:    rem a0, a0, a1
-; CHECK-RV32-NEXT:    pack a0, a0, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psrem_h:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srai a2, a1, 16
+; RV32-NEXT:    srai a3, a0, 16
+; RV32-NEXT:    sext.h a1, a1
+; RV32-NEXT:    sext.h a0, a0
+; RV32-NEXT:    rem a2, a3, a2
+; RV32-NEXT:    rem a0, a0, a1
+; RV32-NEXT:    pack a0, a0, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psrem_h:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    sext.h a2, a1
-; CHECK-RV64-NEXT:    sext.h a3, a0
-; CHECK-RV64-NEXT:    slli a1, a1, 32
-; CHECK-RV64-NEXT:    slli a0, a0, 32
-; CHECK-RV64-NEXT:    remw a2, a3, a2
-; CHECK-RV64-NEXT:    srai a1, a1, 48
-; CHECK-RV64-NEXT:    srai a0, a0, 48
-; CHECK-RV64-NEXT:    remw a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.h a0, a2, a0
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psrem_h:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.h a2, a1
+; RV64-NEXT:    sext.h a3, a0
+; RV64-NEXT:    slli a1, a1, 32
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    remw a2, a3, a2
+; RV64-NEXT:    srai a1, a1, 48
+; RV64-NEXT:    srai a0, a0, 48
+; RV64-NEXT:    remw a0, a0, a1
+; RV64-NEXT:    ppaire.h a0, a2, a0
+; RV64-NEXT:    ret
   %res = srem <2 x i16> %a, %b
   ret <2 x i16> %res
 }
 
 define <4 x i8> @test_psrem_b(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-RV32-LABEL: test_psrem_b:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srai a2, a1, 24
-; CHECK-RV32-NEXT:    srai a3, a0, 24
-; CHECK-RV32-NEXT:    slli a4, a1, 16
-; CHECK-RV32-NEXT:    slli a5, a0, 16
-; CHECK-RV32-NEXT:    rem a3, a3, a2
-; CHECK-RV32-NEXT:    srai a4, a4, 24
-; CHECK-RV32-NEXT:    srai a5, a5, 24
-; CHECK-RV32-NEXT:    rem a2, a5, a4
-; CHECK-RV32-NEXT:    sext.b a4, a1
-; CHECK-RV32-NEXT:    sext.b a5, a0
-; CHECK-RV32-NEXT:    slli a1, a1, 8
-; CHECK-RV32-NEXT:    slli a0, a0, 8
-; CHECK-RV32-NEXT:    rem a4, a5, a4
-; CHECK-RV32-NEXT:    srai a1, a1, 24
-; CHECK-RV32-NEXT:    srai a0, a0, 24
-; CHECK-RV32-NEXT:    rem a5, a0, a1
-; CHECK-RV32-NEXT:    ppaire.db a0, a4, a2
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_psrem_b:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srai a2, a1, 24
+; RV32-NEXT:    srai a3, a0, 24
+; RV32-NEXT:    slli a4, a1, 16
+; RV32-NEXT:    slli a5, a0, 16
+; RV32-NEXT:    rem a3, a3, a2
+; RV32-NEXT:    srai a4, a4, 24
+; RV32-NEXT:    srai a5, a5, 24
+; RV32-NEXT:    rem a2, a5, a4
+; RV32-NEXT:    sext.b a4, a1
+; RV32-NEXT:    sext.b a5, a0
+; RV32-NEXT:    slli a1, a1, 8
+; RV32-NEXT:    slli a0, a0, 8
+; RV32-NEXT:    rem a4, a5, a4
+; RV32-NEXT:    srai a1, a1, 24
+; RV32-NEXT:    srai a0, a0, 24
+; RV32-NEXT:    rem a5, a0, a1
+; RV32-NEXT:    ppaire.db a0, a4, a2
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_psrem_b:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    slli a2, a1, 32
-; CHECK-RV64-NEXT:    slli a3, a0, 32
-; CHECK-RV64-NEXT:    sext.b a4, a1
-; CHECK-RV64-NEXT:    sext.b a5, a0
-; CHECK-RV64-NEXT:    remw a4, a5, a4
-; CHECK-RV64-NEXT:    slli a5, a1, 40
-; CHECK-RV64-NEXT:    srai a2, a2, 56
-; CHECK-RV64-NEXT:    srai a3, a3, 56
-; CHECK-RV64-NEXT:    remw a2, a3, a2
-; CHECK-RV64-NEXT:    slli a3, a0, 40
-; CHECK-RV64-NEXT:    srai a5, a5, 56
-; CHECK-RV64-NEXT:    srai a3, a3, 56
-; CHECK-RV64-NEXT:    remw a3, a3, a5
-; CHECK-RV64-NEXT:    slli a1, a1, 48
-; CHECK-RV64-NEXT:    slli a0, a0, 48
-; CHECK-RV64-NEXT:    srai a1, a1, 56
-; CHECK-RV64-NEXT:    srai a0, a0, 56
-; CHECK-RV64-NEXT:    remw a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.b a1, a3, a2
-; CHECK-RV64-NEXT:    ppaire.b a0, a4, a0
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_psrem_b:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a2, a1, 32
+; RV64-NEXT:    slli a3, a0, 32
+; RV64-NEXT:    sext.b a4, a1
+; RV64-NEXT:    sext.b a5, a0
+; RV64-NEXT:    remw a4, a5, a4
+; RV64-NEXT:    slli a5, a1, 40
+; RV64-NEXT:    srai a2, a2, 56
+; RV64-NEXT:    srai a3, a3, 56
+; RV64-NEXT:    remw a2, a3, a2
+; RV64-NEXT:    slli a3, a0, 40
+; RV64-NEXT:    srai a5, a5, 56
+; RV64-NEXT:    srai a3, a3, 56
+; RV64-NEXT:    remw a3, a3, a5
+; RV64-NEXT:    slli a1, a1, 48
+; RV64-NEXT:    slli a0, a0, 48
+; RV64-NEXT:    srai a1, a1, 56
+; RV64-NEXT:    srai a0, a0, 56
+; RV64-NEXT:    remw a0, a0, a1
+; RV64-NEXT:    ppaire.b a1, a3, a2
+; RV64-NEXT:    ppaire.b a0, a4, a0
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = srem <4 x i8> %a, %b
   ret <4 x i8> %res
 }
 
 define <2 x i16> @test_purem_h(<2 x i16> %a, <2 x i16> %b) {
-; CHECK-RV32-LABEL: test_purem_h:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 16
-; CHECK-RV32-NEXT:    srli a3, a0, 16
-; CHECK-RV32-NEXT:    zext.h a1, a1
-; CHECK-RV32-NEXT:    zext.h a0, a0
-; CHECK-RV32-NEXT:    remu a2, a3, a2
-; CHECK-RV32-NEXT:    remu a0, a0, a1
-; CHECK-RV32-NEXT:    pack a0, a0, a2
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_purem_h:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 16
+; RV32-NEXT:    srli a3, a0, 16
+; RV32-NEXT:    zext.h a1, a1
+; RV32-NEXT:    zext.h a0, a0
+; RV32-NEXT:    remu a2, a3, a2
+; RV32-NEXT:    remu a0, a0, a1
+; RV32-NEXT:    pack a0, a0, a2
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_purem_h:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srliw a2, a1, 16
-; CHECK-RV64-NEXT:    srliw a3, a0, 16
-; CHECK-RV64-NEXT:    zext.h a1, a1
-; CHECK-RV64-NEXT:    zext.h a0, a0
-; CHECK-RV64-NEXT:    remuw a2, a3, a2
-; CHECK-RV64-NEXT:    remuw a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a2
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_purem_h:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srliw a2, a1, 16
+; RV64-NEXT:    srliw a3, a0, 16
+; RV64-NEXT:    zext.h a1, a1
+; RV64-NEXT:    zext.h a0, a0
+; RV64-NEXT:    remuw a2, a3, a2
+; RV64-NEXT:    remuw a0, a0, a1
+; RV64-NEXT:    ppaire.h a0, a0, a2
+; RV64-NEXT:    ret
   %res = urem <2 x i16> %a, %b
   ret <2 x i16> %res
 }
 
 define <4 x i8> @test_purem_b(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-RV32-LABEL: test_purem_b:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    srli a2, a1, 24
-; CHECK-RV32-NEXT:    srli a3, a0, 24
-; CHECK-RV32-NEXT:    slli a4, a1, 16
-; CHECK-RV32-NEXT:    slli a5, a0, 16
-; CHECK-RV32-NEXT:    remu a3, a3, a2
-; CHECK-RV32-NEXT:    srli a4, a4, 24
-; CHECK-RV32-NEXT:    srli a5, a5, 24
-; CHECK-RV32-NEXT:    remu a2, a5, a4
-; CHECK-RV32-NEXT:    zext.b a4, a1
-; CHECK-RV32-NEXT:    zext.b a5, a0
-; CHECK-RV32-NEXT:    slli a1, a1, 8
-; CHECK-RV32-NEXT:    slli a0, a0, 8
-; CHECK-RV32-NEXT:    remu a4, a5, a4
-; CHECK-RV32-NEXT:    srli a1, a1, 24
-; CHECK-RV32-NEXT:    srli a0, a0, 24
-; CHECK-RV32-NEXT:    remu a5, a0, a1
-; CHECK-RV32-NEXT:    ppaire.db a0, a4, a2
-; CHECK-RV32-NEXT:    pack a0, a0, a1
-; CHECK-RV32-NEXT:    ret
+; RV32-LABEL: test_purem_b:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srli a2, a1, 24
+; RV32-NEXT:    srli a3, a0, 24
+; RV32-NEXT:    slli a4, a1, 16
+; RV32-NEXT:    slli a5, a0, 16
+; RV32-NEXT:    remu a3, a3, a2
+; RV32-NEXT:    srli a4, a4, 24
+; RV32-NEXT:    srli a5, a5, 24
+; RV32-NEXT:    remu a2, a5, a4
+; RV32-NEXT:    zext.b a4, a1
+; RV32-NEXT:    zext.b a5, a0
+; RV32-NEXT:    slli a1, a1, 8
+; RV32-NEXT:    slli a0, a0, 8
+; RV32-NEXT:    remu a4, a5, a4
+; RV32-NEXT:    srli a1, a1, 24
+; RV32-NEXT:    srli a0, a0, 24
+; RV32-NEXT:    remu a5, a0, a1
+; RV32-NEXT:    ppaire.db a0, a4, a2
+; RV32-NEXT:    pack a0, a0, a1
+; RV32-NEXT:    ret
 ;
-; CHECK-RV64-LABEL: test_purem_b:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    srliw a2, a1, 24
-; CHECK-RV64-NEXT:    srliw a3, a0, 24
-; CHECK-RV64-NEXT:    slli a4, a1, 40
-; CHECK-RV64-NEXT:    zext.b a5, a1
-; CHECK-RV64-NEXT:    remuw a2, a3, a2
-; CHECK-RV64-NEXT:    zext.b a3, a0
-; CHECK-RV64-NEXT:    remuw a3, a3, a5
-; CHECK-RV64-NEXT:    slli a5, a0, 40
-; CHECK-RV64-NEXT:    srli a4, a4, 56
-; CHECK-RV64-NEXT:    srli a5, a5, 56
-; CHECK-RV64-NEXT:    remuw a4, a5, a4
-; CHECK-RV64-NEXT:    slli a1, a1, 48
-; CHECK-RV64-NEXT:    slli a0, a0, 48
-; CHECK-RV64-NEXT:    srli a1, a1, 56
-; CHECK-RV64-NEXT:    srli a0, a0, 56
-; CHECK-RV64-NEXT:    remuw a0, a0, a1
-; CHECK-RV64-NEXT:    ppaire.b a1, a4, a2
-; CHECK-RV64-NEXT:    ppaire.b a0, a3, a0
-; CHECK-RV64-NEXT:    ppaire.h a0, a0, a1
-; CHECK-RV64-NEXT:    ret
+; RV64-LABEL: test_purem_b:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srliw a2, a1, 24
+; RV64-NEXT:    srliw a3, a0, 24
+; RV64-NEXT:    slli a4, a1, 40
+; RV64-NEXT:    zext.b a5, a1
+; RV64-NEXT:    remuw a2, a3, a2
+; RV64-NEXT:    zext.b a3, a0
+; RV64-NEXT:    remuw a3, a3, a5
+; RV64-NEXT:    slli a5, a0, 40
+; RV64-NEXT:    srli a4, a4, 56
+; RV64-NEXT:    srli a5, a5, 56
+; RV64-NEXT:    remuw a4, a5, a4
+; RV64-NEXT:    slli a1, a1, 48
+; RV64-NEXT:    slli a0, a0, 48
+; RV64-NEXT:    srli a1, a1, 56
+; RV64-NEXT:    srli a0, a0, 56
+; RV64-NEXT:    remuw a0, a0, a1
+; RV64-NEXT:    ppaire.b a1, a4, a2
+; RV64-NEXT:    ppaire.b a0, a3, a0
+; RV64-NEXT:    ppaire.h a0, a0, a1
+; RV64-NEXT:    ret
   %res = urem <4 x i8> %a, %b
   ret <4 x i8> %res
 }
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 999ea39fdb0c..999ea39fdb0c 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll